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intel/isl: Move isl_calc_array_pitch_el_rows higher up
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
parent
c1a70165be
commit
fe13c59c1b
1 changed files with 117 additions and 117 deletions
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@ -711,6 +711,123 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
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}
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}
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/**
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* Calculate the pitch between physical array slices, in units of rows of
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* surface elements.
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*/
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static uint32_t
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isl_calc_array_pitch_el_rows(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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const struct isl_tile_info *tile_info,
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enum isl_dim_layout dim_layout,
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enum isl_array_pitch_span array_pitch_span,
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const struct isl_extent3d *image_align_sa,
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const struct isl_extent4d *phys_level0_sa,
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const struct isl_extent2d *phys_slice0_sa)
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{
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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uint32_t pitch_sa_rows = 0;
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switch (dim_layout) {
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case ISL_DIM_LAYOUT_GEN9_1D:
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/* Each row is an array slice */
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pitch_sa_rows = 1;
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break;
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case ISL_DIM_LAYOUT_GEN4_2D:
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switch (array_pitch_span) {
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case ISL_ARRAY_PITCH_SPAN_COMPACT:
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pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
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break;
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case ISL_ARRAY_PITCH_SPAN_FULL: {
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/* The QPitch equation is found in the Broadwell PRM >> Volume 5:
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* Memory Views >> Common Surface Formats >> Surface Layout >> 2D
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* Surfaces >> Surface Arrays.
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*/
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uint32_t H0_sa = phys_level0_sa->h;
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uint32_t H1_sa = isl_minify(H0_sa, 1);
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uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
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uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
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uint32_t m;
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if (ISL_DEV_GEN(dev) >= 7) {
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/* The QPitch equation changed slightly in Ivybridge. */
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m = 12;
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} else {
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m = 11;
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}
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pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
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if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
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(info->height % 4 == 1)) {
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/* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
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* Graphics Core >> Section 7.18.3.7: Surface Arrays:
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*
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* [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
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* the value calculated in the equation above , for every
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* other odd Surface Height starting from 1 i.e. 1,5,9,13.
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*
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* XXX(chadv): Is the errata natural corollary of the physical
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* layout of interleaved samples?
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*/
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pitch_sa_rows += 4;
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}
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pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
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} /* end case */
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break;
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}
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break;
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case ISL_DIM_LAYOUT_GEN4_3D:
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assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
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pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
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break;
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default:
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unreachable("bad isl_dim_layout");
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break;
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}
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assert(pitch_sa_rows % fmtl->bh == 0);
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uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
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if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
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/*
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* From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
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*
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* "Mip-mapped and arrayed surfaces are supported with MCS buffer
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* layout with these alignments in the RT space: Horizontal
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* Alignment = 128 and Vertical Alignment = 64."
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*
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* From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
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*
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* "For non-multisampled render target's CCS auxiliary surface,
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* QPitch must be computed with Horizontal Alignment = 128 and
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* Surface Vertical Alignment = 256. These alignments are only for
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* CCS buffer and not for associated render target."
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*
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* The first restriction is already handled by isl_choose_image_alignment_el
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* but the second restriction, which is an extension of the first, only
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* applies to qpitch and must be applied here.
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*/
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assert(fmtl->bh == 4);
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pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
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}
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if (ISL_DEV_GEN(dev) >= 9 &&
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info->dim == ISL_SURF_DIM_3D &&
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tile_info->tiling != ISL_TILING_LINEAR) {
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/* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
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*
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* Tile Mode != Linear: This field must be set to an integer multiple
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* of the tile height
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*/
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pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
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}
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return pitch_el_rows;
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}
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/**
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* A variant of isl_calc_phys_slice0_extent_sa() specific to
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* ISL_DIM_LAYOUT_GEN4_2D.
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@ -891,123 +1008,6 @@ isl_calc_phys_slice0_extent_sa(const struct isl_device *dev,
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}
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}
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/**
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* Calculate the pitch between physical array slices, in units of rows of
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* surface elements.
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*/
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static uint32_t
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isl_calc_array_pitch_el_rows(const struct isl_device *dev,
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const struct isl_surf_init_info *restrict info,
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const struct isl_tile_info *tile_info,
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enum isl_dim_layout dim_layout,
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enum isl_array_pitch_span array_pitch_span,
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const struct isl_extent3d *image_align_sa,
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const struct isl_extent4d *phys_level0_sa,
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const struct isl_extent2d *phys_slice0_sa)
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{
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const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
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uint32_t pitch_sa_rows = 0;
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switch (dim_layout) {
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case ISL_DIM_LAYOUT_GEN9_1D:
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/* Each row is an array slice */
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pitch_sa_rows = 1;
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break;
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case ISL_DIM_LAYOUT_GEN4_2D:
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switch (array_pitch_span) {
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case ISL_ARRAY_PITCH_SPAN_COMPACT:
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pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
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break;
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case ISL_ARRAY_PITCH_SPAN_FULL: {
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/* The QPitch equation is found in the Broadwell PRM >> Volume 5:
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* Memory Views >> Common Surface Formats >> Surface Layout >> 2D
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* Surfaces >> Surface Arrays.
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*/
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uint32_t H0_sa = phys_level0_sa->h;
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uint32_t H1_sa = isl_minify(H0_sa, 1);
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uint32_t h0_sa = isl_align_npot(H0_sa, image_align_sa->h);
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uint32_t h1_sa = isl_align_npot(H1_sa, image_align_sa->h);
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uint32_t m;
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if (ISL_DEV_GEN(dev) >= 7) {
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/* The QPitch equation changed slightly in Ivybridge. */
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m = 12;
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} else {
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m = 11;
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}
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pitch_sa_rows = h0_sa + h1_sa + (m * image_align_sa->h);
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if (ISL_DEV_GEN(dev) == 6 && info->samples > 1 &&
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(info->height % 4 == 1)) {
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/* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
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* Graphics Core >> Section 7.18.3.7: Surface Arrays:
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*
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* [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
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* the value calculated in the equation above , for every
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* other odd Surface Height starting from 1 i.e. 1,5,9,13.
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*
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* XXX(chadv): Is the errata natural corollary of the physical
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* layout of interleaved samples?
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*/
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pitch_sa_rows += 4;
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}
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pitch_sa_rows = isl_align_npot(pitch_sa_rows, fmtl->bh);
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} /* end case */
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break;
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}
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break;
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case ISL_DIM_LAYOUT_GEN4_3D:
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assert(array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT);
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pitch_sa_rows = isl_align_npot(phys_slice0_sa->h, image_align_sa->h);
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break;
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default:
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unreachable("bad isl_dim_layout");
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break;
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}
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assert(pitch_sa_rows % fmtl->bh == 0);
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uint32_t pitch_el_rows = pitch_sa_rows / fmtl->bh;
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if (ISL_DEV_GEN(dev) >= 9 && fmtl->txc == ISL_TXC_CCS) {
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/*
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* From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
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*
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* "Mip-mapped and arrayed surfaces are supported with MCS buffer
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* layout with these alignments in the RT space: Horizontal
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* Alignment = 128 and Vertical Alignment = 64."
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*
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* From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
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*
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* "For non-multisampled render target's CCS auxiliary surface,
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* QPitch must be computed with Horizontal Alignment = 128 and
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* Surface Vertical Alignment = 256. These alignments are only for
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* CCS buffer and not for associated render target."
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*
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* The first restriction is already handled by isl_choose_image_alignment_el
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* but the second restriction, which is an extension of the first, only
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* applies to qpitch and must be applied here.
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*/
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assert(fmtl->bh == 4);
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pitch_el_rows = isl_align(pitch_el_rows, 256 / 4);
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}
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if (ISL_DEV_GEN(dev) >= 9 &&
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info->dim == ISL_SURF_DIM_3D &&
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tile_info->tiling != ISL_TILING_LINEAR) {
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/* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
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*
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* Tile Mode != Linear: This field must be set to an integer multiple
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* of the tile height
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*/
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pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
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}
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return pitch_el_rows;
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}
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static uint32_t
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isl_calc_row_pitch_alignment(const struct isl_surf_init_info *surf_info,
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const struct isl_tile_info *tile_info)
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