From fdd351cc8108db7d6922b344f36fbab14a69bbf1 Mon Sep 17 00:00:00 2001
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Mon, 31 Jan 2022 12:43:04 +0000
Subject: [PATCH] anv/genxml/intel/fs: fix binding shader record entry

Bit is flipped compared to all the other packets.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 705395344d25 ("intel/fs: Add support for compiling bindless shaders with resume shaders")
Fixes: c3ac9afca389 ("anv: Create and return ray-tracing pipeline SBT handles")
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078>
(cherry picked from commit 2763a8af5ac3739c677ed7de7bd2a7e60a35f822)
---
 .pick_status.json              | 2 +-
 src/intel/compiler/brw_fs.cpp  | 2 +-
 src/intel/genxml/gen_rt.xml    | 4 ++--
 src/intel/vulkan/anv_private.h | 3 ++-
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 09dfa98c269..001d8eee932 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1102,7 +1102,7 @@
         "description": "anv/genxml/intel/fs: fix binding shader record entry",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "705395344d2541d038326a6f64fbff838b52a71e"
     },
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 54e47904fff..e446d04ac4e 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -10253,7 +10253,7 @@ brw_bsr(const struct intel_device_info *devinfo,
    assert(local_arg_offset % 8 == 0);
 
    return offset |
-          SET_BITS(simd_size > 8, 4, 4) |
+          SET_BITS(simd_size == 8, 4, 4) |
           SET_BITS(local_arg_offset / 8, 2, 0);
 }
 
diff --git a/src/intel/genxml/gen_rt.xml b/src/intel/genxml/gen_rt.xml
index 8ef0ae3c36c..757ab6afff6 100644
--- a/src/intel/genxml/gen_rt.xml
+++ b/src/intel/genxml/gen_rt.xml
@@ -3,8 +3,8 @@
   <struct name="BINDLESS_SHADER_RECORD" length="2">
     <field name="Offset To Local Arguments" start="0" end="2" type="uint"/>
     <field name="Bindless Shader Dispatch Mode" start="4" end="4" type="uint">
-      <value name="SIMD8" value="0"/>
-      <value name="SIMD16" value="1"/>
+      <value name="RT_SIMD16" value="0"/>
+      <value name="RT_SIMD8" value="1"/>
     </field>
     <field name="Kernel Start Pointer" start="6" end="31" type="offset"/>
   </struct>
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 60ed616d904..b205e5b266d 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -3430,7 +3430,8 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
                                                                      \
    (struct GFX_BINDLESS_SHADER_RECORD) {                             \
       .OffsetToLocalArguments = (local_arg_offset) / 8,              \
-      .BindlessShaderDispatchMode = prog_data->simd_size / 16,       \
+      .BindlessShaderDispatchMode =                                  \
+         prog_data->simd_size == 16 ? RT_SIMD16 : RT_SIMD8,          \
       .KernelStartPointer = bin->kernel.offset,                      \
    };                                                                \
 })