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i965: Add a brw_load_register_reg64 helper.

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It appears that we can't do this in a single command (like we do for
MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about
the command length if I try to combine them.  No matter.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Kenneth Graunke 2016-05-04 22:52:52 -07:00
parent 4c71c8a74a
commit fdb6c1887f
2 changed files with 20 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1463,6 +1463,8 @@ void brw_load_register_imm64(struct brw_context *brw,
uint32_t reg, uint64_t imm);
void brw_load_register_reg(struct brw_context *brw, uint32_t src,
uint32_t dest);
void brw_load_register_reg64(struct brw_context *brw, uint32_t src,
uint32_t dest);
void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
uint32_t offset, uint32_t imm);
void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,

18
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -648,6 +648,24 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
ADVANCE_BATCH();
}
/*
* Copies a 64-bit register.
*/
void
brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest)
{
assert(brw->gen >= 8 || brw->is_haswell);
BEGIN_BATCH(6);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
OUT_BATCH(src);
OUT_BATCH(dest);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
OUT_BATCH(src + sizeof(uint32_t));
OUT_BATCH(dest + sizeof(uint32_t));
ADVANCE_BATCH();
}
/*
* Write 32-bits of immediate data to a GPU memory buffer.
*/