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freedreno/a6xx: Add some missing a7xx bits

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Fixes: ad90bf0500 ("freedreno/a6xx: Initial a7xx support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31534>
This commit is contained in:
Rob Clark 2024-10-03 15:29:54 -07:00 • committed by Marge Bot
parent 21beb7a6bd
commit fd8eabdd4b
4 changed files with 36 additions and 7 deletions
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2
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -206,7 +206,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
if (ctx->screen->info->a6xx.has_lpac) {
if (CHIP == A6XX && ctx->screen->info->a6xx.has_lpac) {
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);

3
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -959,6 +959,9 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
OUT_REG(ring, PC_RASTER_CNTL(CHIP));
if (CHIP == A7XX)
OUT_REG(ring, A7XX_PC_RASTER_CNTL_V2());
WRITE(REG_A6XX_PC_MULTIVIEW_CNTL, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);

9
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -251,9 +251,12 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
OUT_REG(ring, SP_CS_BINDLESS_BASE_DESCRIPTOR(CHIP,
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
OUT_REG(ring, A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
if (CHIP == A6XX) {
OUT_REG(ring, A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
}
if (bufso->enabled_mask) {
OUT_PKT(ring, CP_LOAD_STATE6_FRAG,

29
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -592,10 +592,12 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
uint16_t reg_sp_xs_vpc_dst_reg;
uint16_t reg_vpc_xs_pack;
uint16_t reg_vpc_xs_clip_cntl;
uint16_t reg_vpc_xs_clip_cntl_v2;
uint16_t reg_gras_xs_cl_cntl;
uint16_t reg_pc_xs_out_cntl;
uint16_t reg_sp_xs_primitive_cntl;
uint16_t reg_vpc_xs_layer_cntl;
uint16_t reg_vpc_xs_layer_cntl_v2;
uint16_t reg_gras_xs_layer_cntl;
} reg_config[] = {
[MESA_SHADER_VERTEX] = {
@ -603,10 +605,12 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
REG_A6XX_SP_VS_VPC_DST_REG(0),
REG_A6XX_VPC_VS_PACK,
REG_A6XX_VPC_VS_CLIP_CNTL,
REG_A6XX_VPC_VS_CLIP_CNTL_V2,
REG_A6XX_GRAS_VS_CL_CNTL,
REG_A6XX_PC_VS_OUT_CNTL,
REG_A6XX_SP_VS_PRIMITIVE_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL_V2,
REG_A6XX_GRAS_VS_LAYER_CNTL
},
[MESA_SHADER_TESS_CTRL] = {
@ -615,9 +619,11 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
0,
0,
0,
0,
REG_A6XX_PC_HS_OUT_CNTL,
0,
0,
0,
0
},
[MESA_SHADER_TESS_EVAL] = {
@ -625,10 +631,12 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
REG_A6XX_SP_DS_VPC_DST_REG(0),
REG_A6XX_VPC_DS_PACK,
REG_A6XX_VPC_DS_CLIP_CNTL,
REG_A6XX_VPC_DS_CLIP_CNTL_V2,
REG_A6XX_GRAS_DS_CL_CNTL,
REG_A6XX_PC_DS_OUT_CNTL,
REG_A6XX_SP_DS_PRIMITIVE_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL_V2,
REG_A6XX_GRAS_DS_LAYER_CNTL
},
[MESA_SHADER_GEOMETRY] = {
@ -636,10 +644,12 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
REG_A6XX_SP_GS_VPC_DST_REG(0),
REG_A6XX_VPC_GS_PACK,
REG_A6XX_VPC_GS_CLIP_CNTL,
REG_A6XX_VPC_GS_CLIP_CNTL_V2,
REG_A6XX_GRAS_GS_CL_CNTL,
REG_A6XX_PC_GS_OUT_CNTL,
REG_A6XX_SP_GS_PRIMITIVE_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL_V2,
REG_A6XX_GRAS_GS_LAYER_CNTL
},
};
@ -783,6 +793,11 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_PKT4(ring, cfg->reg_vpc_xs_clip_cntl_v2, 1);
OUT_RING(ring, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_PKT4(ring, cfg->reg_gras_xs_cl_cntl, 1);
OUT_RING(ring, A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
@ -820,7 +835,13 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
OUT_PKT4(ring, cfg->reg_vpc_xs_layer_cntl, 1);
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc));
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(0xff));
OUT_PKT4(ring, cfg->reg_vpc_xs_layer_cntl_v2, 1);
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(0xff));
OUT_PKT4(ring, cfg->reg_gras_xs_layer_cntl, 1);
OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) |
@ -884,8 +905,10 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
OUT_RING(ring, 0xff);
}
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
}
uint32_t prim_size = prev_stage_output_size;
if (prim_size > 64)