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freedreno: update register headers
resync w/ rnndb database Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
c2babfccb5
commit
fd59f3ea98
8 changed files with 758 additions and 111 deletions
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@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx.xml ( 30127 bytes, from 2013-05-05 18:29:35)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -236,56 +238,6 @@ enum sq_tex_filter {
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#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
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#define REG_A2XX_CP_RB_BASE 0x000001c0
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#define REG_A2XX_CP_RB_CNTL 0x000001c1
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#define REG_A2XX_CP_RB_RPTR_ADDR 0x000001c3
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#define REG_A2XX_CP_RB_RPTR 0x000001c4
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#define REG_A2XX_CP_RB_WPTR 0x000001c5
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#define REG_A2XX_CP_RB_WPTR_DELAY 0x000001c6
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#define REG_A2XX_CP_RB_RPTR_WR 0x000001c7
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#define REG_A2XX_CP_RB_WPTR_BASE 0x000001c8
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#define REG_A2XX_CP_QUEUE_THRESHOLDS 0x000001d5
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#define REG_A2XX_SCRATCH_UMSK 0x000001dc
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#define REG_A2XX_SCRATCH_ADDR 0x000001dd
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#define REG_A2XX_CP_STATE_DEBUG_INDEX 0x000001ec
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#define REG_A2XX_CP_STATE_DEBUG_DATA 0x000001ed
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#define REG_A2XX_CP_INT_CNTL 0x000001f2
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#define REG_A2XX_CP_INT_STATUS 0x000001f3
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#define REG_A2XX_CP_INT_ACK 0x000001f4
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#define REG_A2XX_CP_ME_CNTL 0x000001f6
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#define REG_A2XX_CP_ME_STATUS 0x000001f7
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#define REG_A2XX_CP_ME_RAM_WADDR 0x000001f8
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#define REG_A2XX_CP_ME_RAM_RADDR 0x000001f9
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#define REG_A2XX_CP_ME_RAM_DATA 0x000001fa
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#define REG_A2XX_CP_DEBUG 0x000001fc
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#define REG_A2XX_CP_CSQ_RB_STAT 0x000001fd
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#define REG_A2XX_CP_CSQ_IB1_STAT 0x000001fe
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#define REG_A2XX_CP_CSQ_IB2_STAT 0x000001ff
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#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
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#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
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@ -338,11 +290,32 @@ enum sq_tex_filter {
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#define REG_A2XX_CP_STAT 0x0000047f
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#define REG_A2XX_SCRATCH_REG0 0x00000578
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#define REG_A2XX_SCRATCH_REG2 0x0000057a
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#define REG_A2XX_RBBM_STATUS 0x000005d0
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#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f
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#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0
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static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
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{
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return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
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}
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#define A2XX_RBBM_STATUS_TC_BUSY 0x00000020
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#define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100
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#define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200
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#define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400
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#define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800
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#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000
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#define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000
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#define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000
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#define A2XX_RBBM_STATUS_MH_BUSY 0x00040000
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#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000
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#define A2XX_RBBM_STATUS_SX_BUSY 0x00200000
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#define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000
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#define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000
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#define A2XX_RBBM_STATUS_PA_BUSY 0x02000000
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#define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000
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#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000
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#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000
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#define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000
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#define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000
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#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
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#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
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@ -358,13 +331,13 @@ static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
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return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
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}
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#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
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static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
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#define REG_A2XX_VSC_PIPE_CONFIG(i0) (0x00000c06 + 0x3*(i0))
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static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
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#define REG_A2XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c07 + 0x3*(i0))
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static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
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#define REG_A2XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c08 + 0x3*(i0))
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static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
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#define REG_A2XX_PC_DEBUG_CNTL 0x00000c38
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@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 42578 bytes, from 2013-06-02 13:10:46)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -130,6 +132,13 @@ enum a3xx_tex_fmt {
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TFMT_NORM_USHORT_5551 = 6,
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TFMT_NORM_USHORT_4444 = 7,
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TFMT_NORM_UINT_X8Z24 = 10,
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TFMT_NORM_UINT_NV12_UV_TILED = 17,
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TFMT_NORM_UINT_NV12_Y_TILED = 19,
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TFMT_NORM_UINT_NV12_UV = 21,
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TFMT_NORM_UINT_NV12_Y = 23,
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TFMT_NORM_UINT_I420_Y = 24,
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TFMT_NORM_UINT_I420_U = 26,
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TFMT_NORM_UINT_I420_V = 27,
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TFMT_NORM_UINT_2_10_10_10 = 41,
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TFMT_NORM_UINT_A8 = 44,
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TFMT_NORM_UINT_L8_A8 = 47,
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@ -207,6 +216,37 @@ enum a3xx_tex_swiz {
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A3XX_TEX_ONE = 5,
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};
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enum a3xx_tex_type {
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A3XX_TEX_1D = 0,
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A3XX_TEX_2D = 1,
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A3XX_TEX_CUBE = 2,
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A3XX_TEX_3D = 3,
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};
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#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
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#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
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#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
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#define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
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#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
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#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
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#define A3XX_INT0_VFD_ERROR 0x00000040
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#define A3XX_INT0_CP_SW_INT 0x00000080
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#define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
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#define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
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#define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
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#define A3XX_INT0_CP_HW_FAULT 0x00000800
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#define A3XX_INT0_CP_DMA 0x00001000
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#define A3XX_INT0_CP_IB2_INT 0x00002000
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#define A3XX_INT0_CP_IB1_INT 0x00004000
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#define A3XX_INT0_CP_RB_INT 0x00008000
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#define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
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#define A3XX_INT0_CP_RB_DONE_TS 0x00020000
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#define A3XX_INT0_CP_VS_DONE_TS 0x00040000
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#define A3XX_INT0_CP_PS_DONE_TS 0x00080000
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#define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
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#define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
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#define A3XX_INT0_MISC_HANG_DETECT 0x01000000
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#define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
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#define REG_A3XX_RBBM_HW_VERSION 0x00000000
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#define REG_A3XX_RBBM_HW_RELEASE 0x00000001
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@ -230,6 +270,27 @@ enum a3xx_tex_swiz {
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#define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
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#define REG_A3XX_RBBM_STATUS 0x00000030
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#define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
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#define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
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#define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
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#define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
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#define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
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#define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
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#define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
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#define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
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#define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
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#define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
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#define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
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#define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
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#define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
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#define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
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#define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
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#define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
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#define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
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#define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
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#define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
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#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
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#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
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#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
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@ -251,20 +312,202 @@ enum a3xx_tex_swiz {
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#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
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#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
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#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
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#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
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#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
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#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
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#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
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#define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
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#define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
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#define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
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#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
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#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
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#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
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#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
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#define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
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#define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
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#define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
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#define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
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#define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
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#define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
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#define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
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#define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
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#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
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#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
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#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
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#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
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#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
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#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
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#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
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#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
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#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
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#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
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#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
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#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
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#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
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#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
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#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
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#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
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#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
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#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
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|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
|
||||
|
||||
#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
|
||||
|
||||
#define REG_A3XX_RBBM_RBBM_CTL 0x00000100
|
||||
|
||||
#define REG_A3XX_RBBM_RBBM_CTL 0x00000100
|
||||
|
||||
#define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
|
||||
|
||||
#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
|
||||
|
|
@ -287,22 +530,20 @@ enum a3xx_tex_swiz {
|
|||
|
||||
#define REG_A3XX_CP_MEQ_DATA 0x000001db
|
||||
|
||||
#define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
|
||||
|
||||
#define REG_A3XX_CP_HW_FAULT 0x0000045c
|
||||
|
||||
#define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
|
||||
|
||||
#define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
|
||||
|
||||
#define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_CP_PROTECT_REG(i0) (0x00000460 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_CP_AHB_FAULT 0x0000054d
|
||||
|
||||
#define REG_A3XX_CP_SCRATCH_REG2 0x0000057a
|
||||
|
||||
#define REG_A3XX_CP_SCRATCH_REG3 0x0000057b
|
||||
|
||||
#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
|
||||
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
|
||||
#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
|
||||
|
|
@ -528,9 +769,9 @@ static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
|
|||
|
||||
#define REG_A3XX_UNKNOWN_20C3 0x000020c3
|
||||
|
||||
#define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
|
||||
|
||||
#define REG_A3XX_RB_MRT_CONTROL(i0) (0x000020c4 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
|
||||
#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
|
||||
#define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
|
||||
#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
|
||||
|
|
@ -553,7 +794,7 @@ static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
|
|||
return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_MRT_BUF_INFO(i0) (0x000020c5 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
|
||||
#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
|
||||
#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
|
||||
|
|
@ -579,7 +820,7 @@ static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
|
|||
return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_MRT_BUF_BASE(i0) (0x000020c6 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
|
||||
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
|
||||
#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
|
||||
static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
|
||||
|
|
@ -587,7 +828,7 @@ static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
|
|||
return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_MRT_BLEND_CONTROL(i0) (0x000020c7 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
|
||||
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
|
||||
#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
|
||||
|
|
@ -627,12 +868,60 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_r
|
|||
#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
|
||||
|
||||
#define REG_A3XX_RB_BLEND_RED 0x000020e4
|
||||
#define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
|
||||
#define A3XX_RB_BLEND_RED_UINT__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
|
||||
}
|
||||
#define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
|
||||
#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
|
||||
#define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
|
||||
#define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
|
||||
}
|
||||
#define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
|
||||
#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
|
||||
#define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
|
||||
#define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
|
||||
}
|
||||
#define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
|
||||
#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
|
||||
#define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
|
||||
#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
|
||||
}
|
||||
#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
|
||||
#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
|
||||
static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
|
||||
{
|
||||
return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_UNKNOWN_20E8 0x000020e8
|
||||
|
||||
|
|
@ -1063,9 +1352,9 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|||
|
||||
#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
|
||||
|
||||
#define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0))
|
||||
static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
|
||||
|
||||
#define REG_A3XX_VFD_FETCH_INSTR_0(i0) (0x00002246 + 0x2*(i0))
|
||||
static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
|
||||
#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
|
||||
#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
|
||||
static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
|
||||
|
|
@ -1092,11 +1381,11 @@ static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
|
|||
return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_VFD_FETCH_INSTR_1(i0) (0x00002247 + 0x2*(i0))
|
||||
static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
|
||||
|
||||
#define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_VFD_DECODE_INSTR(i0) (0x00002266 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
|
||||
#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
|
||||
#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
|
||||
static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
|
||||
|
|
@ -1173,13 +1462,13 @@ static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
|
|||
return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_VPC_VARYING_INTERP_MODE(i0) (0x00002282 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_VPC_VARYING_PS_REPL_MODE(i0) (0x00002286 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
|
||||
|
||||
|
|
@ -1293,9 +1582,9 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
|
|||
return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_SP_VS_OUT_REG(i0) (0x000022c7 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
|
||||
#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
|
||||
#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
|
||||
|
|
@ -1321,9 +1610,9 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
|
|||
return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_SP_VS_VPC_DST_REG(i0) (0x000022d0 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
|
||||
#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
|
||||
|
|
@ -1480,9 +1769,9 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
|
||||
#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
|
||||
|
||||
#define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_SP_FS_MRT_REG(i0) (0x000022f0 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
|
||||
#define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
|
||||
#define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
|
||||
|
|
@ -1491,9 +1780,9 @@ static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
|
|||
}
|
||||
#define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
|
||||
|
||||
#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
|
||||
|
||||
#define REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(i0) (0x000022f4 + 0x1*(i0))
|
||||
static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
|
||||
#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
|
||||
#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
|
||||
static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
|
||||
|
|
@ -1607,9 +1896,9 @@ static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
|
|||
|
||||
#define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
|
||||
|
||||
#define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
|
||||
static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
|
||||
|
||||
#define REG_A3XX_VSC_PIPE_CONFIG(i0) (0x00000c06 + 0x3*(i0))
|
||||
static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
|
||||
#define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
|
||||
#define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
|
||||
static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
|
||||
|
|
@ -1635,26 +1924,46 @@ static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
|
|||
return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c07 + 0x3*(i0))
|
||||
static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
|
||||
|
||||
#define REG_A3XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c08 + 0x3*(i0))
|
||||
static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
|
||||
|
||||
#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
|
||||
|
||||
#define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
|
||||
|
||||
#define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
|
||||
|
||||
#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0C81 0x00000c81
|
||||
|
||||
#define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0))
|
||||
#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
|
||||
|
||||
#define REG_A3XX_GRAS_CL_USER_PLANE_X(i0) (0x00000ca0 + 0x4*(i0))
|
||||
#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
|
||||
|
||||
#define REG_A3XX_GRAS_CL_USER_PLANE_Y(i0) (0x00000ca1 + 0x4*(i0))
|
||||
#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
|
||||
|
||||
#define REG_A3XX_GRAS_CL_USER_PLANE_Z(i0) (0x00000ca2 + 0x4*(i0))
|
||||
#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
|
||||
|
||||
#define REG_A3XX_GRAS_CL_USER_PLANE_W(i0) (0x00000ca3 + 0x4*(i0))
|
||||
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
|
||||
|
||||
#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
|
||||
|
||||
#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
|
||||
|
||||
#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
|
||||
|
||||
#define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0
|
||||
#define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff
|
||||
#define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0
|
||||
|
|
@ -1669,18 +1978,46 @@ static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val)
|
|||
return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0E00 0x00000e00
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0E43 0x00000e43
|
||||
|
||||
#define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
|
||||
|
||||
#define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
|
||||
|
||||
#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
|
||||
|
||||
#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
|
||||
|
||||
#define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
|
||||
|
||||
#define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
|
||||
|
||||
#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
|
||||
|
||||
#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
|
||||
|
||||
#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
|
||||
#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
|
||||
#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
|
||||
|
|
@ -1724,6 +2061,18 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
|
|||
|
||||
#define REG_A3XX_UNKNOWN_0F03 0x00000f03
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
|
||||
|
||||
#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
|
||||
|
||||
#define REG_A3XX_TEX_SAMP_0 0x00000000
|
||||
#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
|
||||
#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
|
||||
|
|
@ -1791,6 +2140,12 @@ static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
|
|||
{
|
||||
return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
|
||||
}
|
||||
#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
|
||||
#define A3XX_TEX_CONST_0_TYPE__SHIFT 30
|
||||
static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
|
||||
{
|
||||
return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_TEX_CONST_1 0x00000001
|
||||
#define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
|
||||
|
|
|
|||
|
|
@ -536,8 +536,8 @@ fd3_emit_restore(struct fd_context *ctx)
|
|||
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
|
||||
OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
|
||||
|
||||
OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E00, 1);
|
||||
OUT_RING(ring, 0x00000000); /* UNKNOWN_0E00 */
|
||||
OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
|
||||
OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
|
||||
|
||||
OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
|
||||
OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
|
||||
|
|
|
|||
|
|
@ -249,7 +249,7 @@ fd3_program_emit(struct fd_ringbuffer *ring,
|
|||
*/
|
||||
for (i = 0; i < 6; i++) {
|
||||
OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER0_SELECT, 1);
|
||||
OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER4_SELECT */
|
||||
OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER0_SELECT */
|
||||
|
||||
OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER4_SELECT, 1);
|
||||
OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER4_SELECT */
|
||||
|
|
|
|||
|
|
@ -306,10 +306,11 @@ fd3_pipe2swap(enum pipe_format format)
|
|||
case PIPE_FORMAT_B8G8R8A8_UNORM:
|
||||
case PIPE_FORMAT_B8G8R8X8_UNORM:
|
||||
return WXYZ;
|
||||
|
||||
case PIPE_FORMAT_R8G8B8A8_UNORM:
|
||||
case PIPE_FORMAT_R8G8B8X8_UNORM:
|
||||
case PIPE_FORMAT_Z24X8_UNORM:
|
||||
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
|
||||
return WZYX;
|
||||
|
||||
default:
|
||||
return WZYX;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
|
|||
git clone git://0x04.net/rules-ng-ng
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 42578 bytes, from 2013-06-02 13:10:46)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -113,5 +115,318 @@ enum adreno_rb_depth_format {
|
|||
DEPTHX_24_8 = 1,
|
||||
};
|
||||
|
||||
enum adreno_mmu_clnt_beh {
|
||||
BEH_NEVR = 0,
|
||||
BEH_TRAN_RNG = 1,
|
||||
BEH_TRAN_FLT = 2,
|
||||
};
|
||||
|
||||
#define REG_AXXX_MH_MMU_CONFIG 0x00000040
|
||||
#define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
|
||||
#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
|
||||
#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
|
||||
#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
|
||||
#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
|
||||
#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
|
||||
#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_MH_MMU_VA_RANGE 0x00000041
|
||||
|
||||
#define REG_AXXX_MH_MMU_PT_BASE 0x00000042
|
||||
|
||||
#define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043
|
||||
|
||||
#define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044
|
||||
|
||||
#define REG_AXXX_MH_MMU_INVALIDATE 0x00000045
|
||||
|
||||
#define REG_AXXX_MH_MMU_MPU_BASE 0x00000046
|
||||
|
||||
#define REG_AXXX_MH_MMU_MPU_END 0x00000047
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
|
||||
#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
|
||||
#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
|
||||
#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
|
||||
#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
|
||||
#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
|
||||
#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
|
||||
#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
|
||||
}
|
||||
#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
|
||||
#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
|
||||
static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR 0x000001c4
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR 0x000001c5
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
|
||||
|
||||
#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
|
||||
|
||||
#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
|
||||
|
||||
#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
|
||||
}
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
|
||||
}
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
|
||||
#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
|
||||
|
||||
#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
|
||||
#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
|
||||
#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
|
||||
#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
|
||||
#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
|
||||
#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
|
||||
#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_SCRATCH_UMSK 0x000001dc
|
||||
#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
|
||||
#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
|
||||
static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
|
||||
}
|
||||
#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
|
||||
#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
|
||||
static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_SCRATCH_ADDR 0x000001dd
|
||||
|
||||
#define REG_AXXX_CP_ME_RDADDR 0x000001ea
|
||||
|
||||
#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
|
||||
|
||||
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
|
||||
|
||||
#define REG_AXXX_CP_INT_CNTL 0x000001f2
|
||||
|
||||
#define REG_AXXX_CP_INT_STATUS 0x000001f3
|
||||
|
||||
#define REG_AXXX_CP_INT_ACK 0x000001f4
|
||||
|
||||
#define REG_AXXX_CP_ME_CNTL 0x000001f6
|
||||
|
||||
#define REG_AXXX_CP_ME_STATUS 0x000001f7
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
|
||||
|
||||
#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
|
||||
|
||||
#define REG_AXXX_CP_DEBUG 0x000001fc
|
||||
#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
|
||||
#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
|
||||
#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
|
||||
#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
|
||||
#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
|
||||
#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
|
||||
#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
|
||||
#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
|
||||
|
||||
#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
|
||||
#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
|
||||
#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
|
||||
#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
|
||||
#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
|
||||
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
|
||||
}
|
||||
#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
|
||||
#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
|
||||
|
||||
#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
|
||||
|
||||
#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
|
||||
|
||||
|
||||
#endif /* ADRENO_COMMON_XML */
|
||||
|
|
|
|||
|
|
@ -8,10 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
|
|||
git clone git://0x04.net/rules-ng-ng
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 42578 bytes, from 2013-06-02 13:10:46)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 3094 bytes, from 2013-05-05 18:29:22)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
#include "pipe/p_format.h"
|
||||
#include "util/u_debug.h"
|
||||
#include "util/u_math.h"
|
||||
#include "util/u_half.h"
|
||||
|
||||
#include "adreno_common.xml.h"
|
||||
#include "adreno_pm4.xml.h"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue