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anv: remove duplicate pipe_control workaround

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Commit a603cc0633 ("anv: move some pc was to
batch_emit_pipe_control_write") moved some WAs from
emit_apply_pipe_flushes() to batch_emit_pipe_control_write(), but it
turns out one of them was already there since cf7e1f3817 ("anv,
iris: add missing CS_STALL bit for GPGPU texture invalidation").

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31412>
This commit is contained in:
Paulo Zanoni 2024-08-05 16:09:01 -07:00 • committed by Marge Bot
parent 242da61b9d
commit fd4a44430c
1 changed files with 0 additions and 14 deletions
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14
src/intel/vulkan/genX_cmd_buffer.c
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@ -2515,20 +2515,6 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch,
if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT))
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe);
#if GFX_VER >= 9 && GFX_VER <= 11
/* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
*
* "Workaround : “CS Stall” bit in PIPE_CONTROL command must be
* always set for GPGPU workloads when “Texture Cache
* Invalidation Enable” bit is set".
*
* Workaround stopped appearing in TGL PRMs.
*/
if (current_pipeline == GPGPU &&
(bits & ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT))
bits |= ANV_PIPE_CS_STALL_BIT;
#endif
anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) {
#if GFX_VERx10 >= 125
pipe.UntypedDataPortCacheFlushEnable =