From fd3f9a152cb178793bf809a4dbe7b7ed1d98d2ec Mon Sep 17 00:00:00 2001 From: Friedrich Vock Date: Wed, 15 May 2024 13:37:12 +0200 Subject: [PATCH] radeonsi: Use max_se instead of num_se where appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Scratch allocation needs to happen using max_se, otherwise there can be hangs. Cc: mesa-stable Reviewed-by: Marek Olšák Part-of: (cherry picked from commit 18c736bcfc55b8fa309ede02332b9c7a2ca22e78) --- .pick_status.json | 2 +- src/amd/common/ac_shader_util.c | 2 +- src/gallium/drivers/radeonsi/si_state.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index bfe6a2c0906..2fa6d693eae 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -364,7 +364,7 @@ "description": "radeonsi: Use max_se instead of num_se where appropriate", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c index 65772950ccd..d67c5a8b065 100644 --- a/src/amd/common/ac_shader_util.c +++ b/src/amd/common/ac_shader_util.c @@ -1168,7 +1168,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, unsigned max_scratch_waves = info->max_scratch_waves; if (info->gfx_level >= GFX11) - max_scratch_waves /= info->num_se; /* WAVES is per SE */ + max_scratch_waves /= info->max_se; /* WAVES is per SE */ /* TODO: We could decrease WAVES to make the whole buffer fit into the infinity cache. */ *tmpring_size = S_0286E8_WAVES(max_scratch_waves) | diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 67099b1e366..6d6e31b82a5 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -6291,7 +6291,7 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) for (unsigned i = 0; i < 4; ++i) si_pm4_set_reg(pm4, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 + i * 4, - i < sscreen->info.num_se ? compute_cu_en : 0x0); + i < sscreen->info.max_se ? compute_cu_en : 0x0); si_pm4_set_reg(pm4, R_00B890_COMPUTE_USER_ACCUM_0, 0); si_pm4_set_reg(pm4, R_00B894_COMPUTE_USER_ACCUM_1, 0); @@ -6301,7 +6301,7 @@ static void gfx10_init_gfx_preamble_state(struct si_context *sctx) if (sctx->gfx_level >= GFX11) { for (unsigned i = 4; i < 8; ++i) si_pm4_set_reg(pm4, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4 + (i - 4) * 4, - i < sscreen->info.num_se ? compute_cu_en : 0x0); + i < sscreen->info.max_se ? compute_cu_en : 0x0); /* How many threads should go to 1 SE before moving onto the next. Think of GL1 cache hits. * Only these values are valid: 0 (disabled), 64, 128, 256, 512