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intel: Handle decode of PIPE_CONTROL instructions.

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This commit is contained in:
Eric Anholt 2010-05-25 14:48:34 -07:00
parent ddb10c3e60
commit fd3425fdff
1 changed files with 27 additions and 0 deletions
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27
src/mesa/drivers/dri/intel/intel_decode.c
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@ -1407,6 +1407,7 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures)
{
unsigned int opcode, len;
int i;
char *desc1;
struct {
uint32_t opcode;
@ -1622,6 +1623,32 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, int *failures)
return len;
case 0x7a00:
len = (data[0] & 0xff) + 2;
if (len != 4)
fprintf(out, "Bad count in PIPE_CONTROL\n");
if (count < len)
BUFFER_FAIL(count, len, "PIPE_CONTROL");
switch ((data[0] >> 14) & 0x3) {
case 0: desc1 = "no write"; break;
case 1: desc1 = "qword write"; break;
case 2: desc1 = "PS_DEPTH_COUNT write"; break;
case 3: desc1 = "TIMESTAMP write"; break;
}
instr_out(data, hw_offset, 0,
"PIPE_CONTROL: %s, %sdepth stall, %sRC write flush, "
"%sinst flush, %stexture flush\n",
desc1,
data[0] & (1 << 13) ? "" : "no ",
data[0] & (1 << 12) ? "" : "no ",
data[0] & (1 << 11) ? "" : "no ",
data[0] & (1 << 9) ? "" : "no ");
instr_out(data, hw_offset, 1, "destination address\n");
instr_out(data, hw_offset, 2, "immediate dword low\n");
instr_out(data, hw_offset, 3, "immediate dword high\n");
return len;
case 0x7b00:
len = (data[0] & 0xff) + 2;
if (len != 6)