fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-30 18:40:13 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radeonsi/vce: Fix bitstream buffer size

Browse source 
On old VCE this was being rejected by kernel because the size here
was the buffer size, but the bitstream buffer address includes the
offset.

Fixes: 901aafb030 ("radeonsi/vce: Support raw packed headers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13128
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34894>
This commit is contained in:
David Rosca 2025-05-09 11:56:34 +02:00 • committed by Marge Bot
parent f27d062abc
commit fd1480c3df
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/radeonsi/radeon_vce.c
View file

@ -373,7 +373,7 @@ static void encode(struct rvce_encoder *enc)
RVCE_BEGIN(0x05000004); // video bitstream buffer
RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, enc->bs_offset); // videoBitstreamRingAddressHi/Lo
RVCE_CS(enc->bs_size); // videoBitstreamRingSize
RVCE_CS(enc->bs_size - enc->bs_offset); // videoBitstreamRingSize
RVCE_END();
if (enc->dual_pipe) {