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r300: remove irrelevant opcodes in ntr
Remove anything unsupported by the hardware, including the 64bit variants. Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Filip Gawin <filip.gawin@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23437>
This commit is contained in:
Pavel Ondračka
Marge Bot
parent
98ae4efcec
commit
fcefbf9599
1 changed files with 26 additions and 228 deletions
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@ -1439,8 +1439,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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struct ureg_src src[4];
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struct ureg_dst dst;
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unsigned i;
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int dst_64 = instr->def.bit_size == 64;
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int src_64 = nir_src_bit_size(instr->src[0].src) == 64;
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int num_srcs = nir_op_infos[instr->op].num_inputs;
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/* Don't try to translate folded fsat since their source won't be valid */
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@ -1457,132 +1455,38 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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dst = ntr_get_alu_dest(c, &instr->def);
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static enum tgsi_opcode op_map[][2] = {
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[nir_op_mov] = { TGSI_OPCODE_MOV, TGSI_OPCODE_MOV },
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static enum tgsi_opcode op_map[] = {
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[nir_op_mov] = TGSI_OPCODE_MOV,
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/* fabs/fneg 32-bit are special-cased below. */
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[nir_op_fabs] = { 0, TGSI_OPCODE_DABS },
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[nir_op_fneg] = { 0, TGSI_OPCODE_DNEG },
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[nir_op_fdot2_replicated] = TGSI_OPCODE_DP2,
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[nir_op_fdot3_replicated] = TGSI_OPCODE_DP3,
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[nir_op_fdot4_replicated] = TGSI_OPCODE_DP4,
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[nir_op_ffloor] = TGSI_OPCODE_FLR,
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[nir_op_ffract] = TGSI_OPCODE_FRC,
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[nir_op_fceil] = TGSI_OPCODE_CEIL,
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[nir_op_fround_even] = TGSI_OPCODE_ROUND,
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[nir_op_fdot2] = { TGSI_OPCODE_DP2 },
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[nir_op_fdot3] = { TGSI_OPCODE_DP3 },
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[nir_op_fdot4] = { TGSI_OPCODE_DP4 },
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[nir_op_fdot2_replicated] = { TGSI_OPCODE_DP2 },
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[nir_op_fdot3_replicated] = { TGSI_OPCODE_DP3 },
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[nir_op_fdot4_replicated] = { TGSI_OPCODE_DP4 },
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[nir_op_ffloor] = { TGSI_OPCODE_FLR, TGSI_OPCODE_DFLR },
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[nir_op_ffract] = { TGSI_OPCODE_FRC, TGSI_OPCODE_DFRAC },
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[nir_op_fceil] = { TGSI_OPCODE_CEIL, TGSI_OPCODE_DCEIL },
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[nir_op_fround_even] = { TGSI_OPCODE_ROUND, TGSI_OPCODE_DROUND },
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[nir_op_fdiv] = { TGSI_OPCODE_DIV, TGSI_OPCODE_DDIV },
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[nir_op_idiv] = { TGSI_OPCODE_IDIV, TGSI_OPCODE_I64DIV },
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[nir_op_udiv] = { TGSI_OPCODE_UDIV, TGSI_OPCODE_U64DIV },
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[nir_op_slt] = TGSI_OPCODE_SLT,
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[nir_op_sge] = TGSI_OPCODE_SGE,
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[nir_op_seq] = TGSI_OPCODE_SEQ,
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[nir_op_sne] = TGSI_OPCODE_SNE,
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[nir_op_frcp] = { 0, TGSI_OPCODE_DRCP },
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[nir_op_frsq] = { 0, TGSI_OPCODE_DRSQ },
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[nir_op_fsqrt] = { 0, TGSI_OPCODE_DSQRT },
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[nir_op_ftrunc] = TGSI_OPCODE_TRUNC,
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[nir_op_fddx] = TGSI_OPCODE_DDX,
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[nir_op_fddy] = TGSI_OPCODE_DDY,
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[nir_op_fddx_coarse] = TGSI_OPCODE_DDX,
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[nir_op_fddy_coarse] = TGSI_OPCODE_DDY,
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[nir_op_fadd] = TGSI_OPCODE_ADD,
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[nir_op_fmul] = TGSI_OPCODE_MUL,
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/* The conversions will have one combination of src and dst bitsize. */
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[nir_op_f2f32] = { 0, TGSI_OPCODE_D2F },
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[nir_op_f2f64] = { TGSI_OPCODE_F2D },
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[nir_op_i2i64] = { TGSI_OPCODE_I2I64 },
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[nir_op_f2i32] = { TGSI_OPCODE_F2I, TGSI_OPCODE_D2I },
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[nir_op_f2i64] = { TGSI_OPCODE_F2I64, TGSI_OPCODE_D2I64 },
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[nir_op_f2u32] = { TGSI_OPCODE_F2U, TGSI_OPCODE_D2U },
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[nir_op_f2u64] = { TGSI_OPCODE_F2U64, TGSI_OPCODE_D2U64 },
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[nir_op_i2f32] = { TGSI_OPCODE_I2F, TGSI_OPCODE_I642F },
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[nir_op_i2f64] = { TGSI_OPCODE_I2D, TGSI_OPCODE_I642D },
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[nir_op_u2f32] = { TGSI_OPCODE_U2F, TGSI_OPCODE_U642F },
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[nir_op_u2f64] = { TGSI_OPCODE_U2D, TGSI_OPCODE_U642D },
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[nir_op_slt] = { TGSI_OPCODE_SLT },
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[nir_op_sge] = { TGSI_OPCODE_SGE },
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[nir_op_seq] = { TGSI_OPCODE_SEQ },
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[nir_op_sne] = { TGSI_OPCODE_SNE },
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[nir_op_flt32] = { TGSI_OPCODE_FSLT, TGSI_OPCODE_DSLT },
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[nir_op_fge32] = { TGSI_OPCODE_FSGE, TGSI_OPCODE_DSGE },
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[nir_op_feq32] = { TGSI_OPCODE_FSEQ, TGSI_OPCODE_DSEQ },
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[nir_op_fneu32] = { TGSI_OPCODE_FSNE, TGSI_OPCODE_DSNE },
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[nir_op_ilt32] = { TGSI_OPCODE_ISLT, TGSI_OPCODE_I64SLT },
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[nir_op_ige32] = { TGSI_OPCODE_ISGE, TGSI_OPCODE_I64SGE },
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[nir_op_ieq32] = { TGSI_OPCODE_USEQ, TGSI_OPCODE_U64SEQ },
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[nir_op_ine32] = { TGSI_OPCODE_USNE, TGSI_OPCODE_U64SNE },
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[nir_op_ult32] = { TGSI_OPCODE_USLT, TGSI_OPCODE_U64SLT },
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[nir_op_uge32] = { TGSI_OPCODE_USGE, TGSI_OPCODE_U64SGE },
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[nir_op_iabs] = { TGSI_OPCODE_IABS, TGSI_OPCODE_I64ABS },
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[nir_op_ineg] = { TGSI_OPCODE_INEG, TGSI_OPCODE_I64NEG },
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[nir_op_fsign] = { TGSI_OPCODE_SSG, TGSI_OPCODE_DSSG },
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[nir_op_isign] = { TGSI_OPCODE_ISSG, TGSI_OPCODE_I64SSG },
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[nir_op_ftrunc] = { TGSI_OPCODE_TRUNC, TGSI_OPCODE_DTRUNC },
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[nir_op_fddx] = { TGSI_OPCODE_DDX },
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[nir_op_fddy] = { TGSI_OPCODE_DDY },
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[nir_op_fddx_coarse] = { TGSI_OPCODE_DDX },
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[nir_op_fddy_coarse] = { TGSI_OPCODE_DDY },
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[nir_op_fddx_fine] = { TGSI_OPCODE_DDX_FINE },
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[nir_op_fddy_fine] = { TGSI_OPCODE_DDY_FINE },
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[nir_op_pack_half_2x16] = { TGSI_OPCODE_PK2H },
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[nir_op_unpack_half_2x16] = { TGSI_OPCODE_UP2H },
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[nir_op_ibitfield_extract] = { TGSI_OPCODE_IBFE },
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[nir_op_ubitfield_extract] = { TGSI_OPCODE_UBFE },
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[nir_op_bitfield_insert] = { TGSI_OPCODE_BFI },
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[nir_op_bitfield_reverse] = { TGSI_OPCODE_BREV },
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[nir_op_bit_count] = { TGSI_OPCODE_POPC },
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[nir_op_ifind_msb] = { TGSI_OPCODE_IMSB },
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[nir_op_ufind_msb] = { TGSI_OPCODE_UMSB },
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[nir_op_find_lsb] = { TGSI_OPCODE_LSB },
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[nir_op_fadd] = { TGSI_OPCODE_ADD, TGSI_OPCODE_DADD },
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[nir_op_iadd] = { TGSI_OPCODE_UADD, TGSI_OPCODE_U64ADD },
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[nir_op_fmul] = { TGSI_OPCODE_MUL, TGSI_OPCODE_DMUL },
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[nir_op_imul] = { TGSI_OPCODE_UMUL, TGSI_OPCODE_U64MUL },
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[nir_op_imod] = { TGSI_OPCODE_MOD, TGSI_OPCODE_I64MOD },
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[nir_op_umod] = { TGSI_OPCODE_UMOD, TGSI_OPCODE_U64MOD },
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[nir_op_imul_high] = { TGSI_OPCODE_IMUL_HI },
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[nir_op_umul_high] = { TGSI_OPCODE_UMUL_HI },
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[nir_op_ishl] = { TGSI_OPCODE_SHL, TGSI_OPCODE_U64SHL },
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[nir_op_ishr] = { TGSI_OPCODE_ISHR, TGSI_OPCODE_I64SHR },
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[nir_op_ushr] = { TGSI_OPCODE_USHR, TGSI_OPCODE_U64SHR },
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/* These bitwise ops don't care about 32 vs 64 types, so they have the
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* same TGSI op.
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*/
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[nir_op_inot] = { TGSI_OPCODE_NOT, TGSI_OPCODE_NOT },
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[nir_op_iand] = { TGSI_OPCODE_AND, TGSI_OPCODE_AND },
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[nir_op_ior] = { TGSI_OPCODE_OR, TGSI_OPCODE_OR },
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[nir_op_ixor] = { TGSI_OPCODE_XOR, TGSI_OPCODE_XOR },
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[nir_op_fmin] = { TGSI_OPCODE_MIN, TGSI_OPCODE_DMIN },
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[nir_op_imin] = { TGSI_OPCODE_IMIN, TGSI_OPCODE_I64MIN },
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[nir_op_umin] = { TGSI_OPCODE_UMIN, TGSI_OPCODE_U64MIN },
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[nir_op_fmax] = { TGSI_OPCODE_MAX, TGSI_OPCODE_DMAX },
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[nir_op_imax] = { TGSI_OPCODE_IMAX, TGSI_OPCODE_I64MAX },
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[nir_op_umax] = { TGSI_OPCODE_UMAX, TGSI_OPCODE_U64MAX },
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[nir_op_ffma] = { TGSI_OPCODE_MAD, TGSI_OPCODE_DMAD },
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[nir_op_ldexp] = { TGSI_OPCODE_LDEXP, 0 },
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[nir_op_fmin] = TGSI_OPCODE_MIN,
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[nir_op_fmax] = TGSI_OPCODE_MAX,
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[nir_op_ffma] = TGSI_OPCODE_MAD,
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};
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if (src_64 && !dst_64) {
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if (num_srcs == 2 || nir_op_infos[instr->op].output_type == nir_type_bool32) {
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/* TGSI's 64 bit compares storing to 32-bit are weird and write .xz instead
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* of .xy.
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*/
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assert(!(dst.WriteMask & TGSI_WRITEMASK_YW));
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} else {
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/* TGSI 64bit-to-32-bit conversions only generate results in the .xy
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* channels and will need to get fixed up.
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*/
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assert(!(dst.WriteMask & TGSI_WRITEMASK_ZW));
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}
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}
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bool table_op64 = src_64;
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if (instr->op < ARRAY_SIZE(op_map) && op_map[instr->op][table_op64] != 0) {
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if (instr->op < ARRAY_SIZE(op_map) && op_map[instr->op] > 0) {
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/* The normal path for NIR to TGSI ALU op translation */
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ntr_insn(c, op_map[instr->op][table_op64],
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ntr_insn(c, op_map[instr->op],
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dst, src[0], src[1], src[2], src[3]);
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} else {
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/* Special cases for NIR to TGSI ALU op translation. */
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@ -1592,21 +1496,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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*/
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switch (instr->op) {
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case nir_op_u2u64:
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ntr_AND(c, dst, ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y),
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ureg_imm4u(c->ureg, ~0, 0, ~0, 0));
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break;
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case nir_op_i2i32:
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case nir_op_u2u32:
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assert(src_64);
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ntr_MOV(c, dst, ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X));
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break;
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case nir_op_fabs:
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/* Try to eliminate */
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if (!c->options->lower_fabs && nir_legacy_float_mod_folds(instr))
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@ -1619,12 +1508,7 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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break;
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case nir_op_fsat:
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if (dst_64) {
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ntr_MIN(c, dst, src[0], ntr_64bit_1f(c));
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ntr_MAX(c, dst, ureg_src(dst), ureg_imm1u(c->ureg, 0));
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} else {
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ntr_MOV(c, ureg_saturate(dst), src[0]);
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}
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ntr_MOV(c, ureg_saturate(dst), src[0]);
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break;
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case nir_op_fneg:
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@ -1640,54 +1524,21 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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* of src channels to dst.
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*/
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case nir_op_frcp:
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assert(!dst_64);
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ntr_emit_scalar(c, TGSI_OPCODE_RCP, dst, src[0], ureg_src_undef());
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break;
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case nir_op_frsq:
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assert(!dst_64);
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ntr_emit_scalar(c, TGSI_OPCODE_RSQ, dst, src[0], ureg_src_undef());
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break;
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case nir_op_fsqrt:
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assert(!dst_64);
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ntr_emit_scalar(c, TGSI_OPCODE_SQRT, dst, src[0], ureg_src_undef());
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break;
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case nir_op_fexp2:
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assert(!dst_64);
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ntr_emit_scalar(c, TGSI_OPCODE_EX2, dst, src[0], ureg_src_undef());
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break;
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case nir_op_flog2:
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assert(!dst_64);
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ntr_emit_scalar(c, TGSI_OPCODE_LG2, dst, src[0], ureg_src_undef());
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break;
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case nir_op_b2f32:
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ntr_AND(c, dst, src[0], ureg_imm1f(c->ureg, 1.0));
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break;
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case nir_op_b2f64:
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ntr_AND(c, dst,
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ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y),
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ntr_64bit_1f(c));
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break;
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case nir_op_b2i32:
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ntr_AND(c, dst, src[0], ureg_imm1u(c->ureg, 1));
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break;
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case nir_op_b2i64:
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ntr_AND(c, dst,
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ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y),
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ureg_imm4u(c->ureg, 1, 0, 1, 0));
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break;
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case nir_op_fsin:
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ntr_emit_scalar(c, TGSI_OPCODE_SIN, dst, src[0], ureg_src_undef());
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break;
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@ -1697,15 +1548,9 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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break;
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case nir_op_fsub:
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assert(!dst_64);
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ntr_ADD(c, dst, src[0], ureg_negate(src[1]));
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break;
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case nir_op_isub:
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assert(!dst_64);
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ntr_UADD(c, dst, src[0], ureg_negate(src[1]));
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break;
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case nir_op_fmod:
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unreachable("should be handled by .lower_fmod = true");
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break;
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@ -1718,40 +1563,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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ntr_LRP(c, dst, src[2], src[1], src[0]);
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break;
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case nir_op_pack_64_2x32_split:
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ntr_MOV(c, ureg_writemask(dst, TGSI_WRITEMASK_XZ),
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ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y));
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ntr_MOV(c, ureg_writemask(dst, TGSI_WRITEMASK_YW),
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ureg_swizzle(src[1],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y));
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break;
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case nir_op_unpack_64_2x32_split_x:
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ntr_MOV(c, dst, ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z,
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_Z));
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break;
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case nir_op_unpack_64_2x32_split_y:
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ntr_MOV(c, dst, ureg_swizzle(src[0],
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_W,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_W));
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break;
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case nir_op_b32csel:
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if (nir_src_bit_size(instr->src[1].src) == 64) {
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ntr_UCMP(c, dst, ureg_swizzle(src[0],
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TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
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TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y),
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src[1], src[2]);
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} else {
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ntr_UCMP(c, dst, src[0], src[1], src[2]);
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}
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break;
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case nir_op_fcsel:
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/* If CMP isn't supported, then the flags that enable NIR to generate
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* this opcode should also not be set.
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@ -1781,19 +1592,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
|
|||
ntr_CMP(c, dst, src[0], src[2], src[1]);
|
||||
break;
|
||||
|
||||
case nir_op_frexp_sig:
|
||||
case nir_op_frexp_exp:
|
||||
unreachable("covered by nir_lower_frexp()");
|
||||
break;
|
||||
|
||||
case nir_op_ldexp:
|
||||
assert(dst_64); /* 32bit handled in table. */
|
||||
ntr_DLDEXP(c, dst, src[0],
|
||||
ureg_swizzle(src[1],
|
||||
TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
|
||||
TGSI_SWIZZLE_Y, TGSI_SWIZZLE_Y));
|
||||
break;
|
||||
|
||||
case nir_op_vec4:
|
||||
case nir_op_vec3:
|
||||
case nir_op_vec2:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue