diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 57459a36727..05398b4ba4c 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -291,22 +291,8 @@ radv_use_dcc_for_image(struct radv_device *device, struct radv_image *image,
 bool
 radv_image_use_dcc_image_stores(const struct radv_device *device, const struct radv_image *image)
 {
-   /* DCC image stores is only available for GFX10+. */
-   if (device->physical_device->rad_info.chip_class < GFX10)
-      return false;
-
-   /* DCC image stores require the following settings:
-    * - INDEPENDENT_64B_BLOCKS = 0
-    * - INDEPENDENT_128B_BLOCKS = 1
-    * - MAX_COMPRESSED_BLOCK_SIZE = 128B
-    * - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
-    *
-    * The same limitations apply to SDMA compressed stores because
-    * SDMA uses the same DCC codec.
-    */
-   return !image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks  &&
-           image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks &&
-           image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
+   return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.chip_class,
+                                               &image->planes[0].surface);
 }
 
 /*