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freedreno/regs: document CS shared storage size bit

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Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5797>
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Jonathan Marek 2020-07-07 22:31:44 -04:00 • committed by Marge Bot
parent deefebc55b
commit fcac0b4fc9
1 changed files with 10 additions and 1 deletions
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11
src/freedreno/registers/a6xx.xml
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@ -3193,7 +3193,16 @@ to upconvert to 32b float internally?
<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
<!-- set for compute shaders, always 0x41 -->
<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint">
<doc>
bit 0 seems to toggle between 2k and 32k of shared storage
the ldl/stl offset seems to be rewritten to 0 when it is beyond
this limit. This is different from ldlw/stlw, which wraps at
64k (and has 36k of storage on A640 - reads between 36k-64k
always return 0)
</doc>
<bitfield name="SHARED_SIZE_2K" pos="0" type="uint"/>
</reg32>
<!-- set for compute shaders, always 0x0 -->
<reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>