From fc56823cf0bb1936f8ed18dc3e8826c5ec008924 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 13 Jan 2025 07:20:33 -0800 Subject: [PATCH] radv: change the BASE_HI field for VGT_TF_MEMORY_BASE_HI on GFX12 It's similar but less confusing. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 2005364f812..dba9770c30c 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -408,7 +408,7 @@ radv_emit_tess_factor_ring(struct radv_device *device, struct radeon_cmdbuf *cs, radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8); if (pdev->info.gfx_level >= GFX12) { - radeon_set_uconfig_reg(cs, R_03099C_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(tf_va >> 40)); + radeon_set_uconfig_reg(cs, R_03099C_VGT_TF_MEMORY_BASE_HI, S_03099C_BASE_HI(tf_va >> 40)); } else if (pdev->info.gfx_level >= GFX10) { radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(tf_va >> 40)); } else if (pdev->info.gfx_level == GFX9) {