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anv: dynamic color write mask
This affects following packets: 3DSTATE_BLEND_STATE_POINTERS Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18879>
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3 changed files with 7 additions and 16 deletions
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@ -2302,14 +2302,6 @@ anv_graphics_pipeline_init(struct anv_graphics_pipeline *pipeline,
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pipeline->patch_control_points =
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pipeline->patch_control_points =
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state->ts != NULL ? state->ts->patch_control_points : 0;
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state->ts != NULL ? state->ts->patch_control_points : 0;
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/* Store the color write masks, to be merged with color write enable if
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* dynamic.
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*/
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if (state->cb != NULL) {
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for (unsigned i = 0; i < state->cb->attachment_count; i++)
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pipeline->color_comp_writes[i] = state->cb->attachments[i].write_mask;
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}
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return VK_SUCCESS;
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return VK_SUCCESS;
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}
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}
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@ -2954,8 +2954,6 @@ struct anv_graphics_pipeline {
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uint32_t patch_control_points;
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uint32_t patch_control_points;
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uint32_t rasterization_samples;
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uint32_t rasterization_samples;
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VkColorComponentFlags color_comp_writes[MAX_RTS];
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uint32_t view_mask;
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uint32_t view_mask;
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uint32_t instance_multiplier;
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uint32_t instance_multiplier;
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@ -3072,7 +3070,7 @@ anv_cmd_buffer_all_color_write_masked(const struct anv_cmd_buffer *cmd_buffer)
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/* Or all write masks are empty */
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/* Or all write masks are empty */
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for (uint32_t i = 0; i < state->color_att_count; i++) {
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for (uint32_t i = 0; i < state->color_att_count; i++) {
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if (state->pipeline->color_comp_writes[i] != 0)
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if (dyn->cb.attachments[i].write_mask != 0)
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return false;
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return false;
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}
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}
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@ -532,7 +532,8 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_LOGIC_OP_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE)) {
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE) ||
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BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES)) {
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const uint8_t color_writes = dyn->cb.color_write_enables;
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const uint8_t color_writes = dyn->cb.color_write_enables;
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const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
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const struct anv_cmd_graphics_state *state = &cmd_buffer->state.gfx;
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bool has_writeable_rt =
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bool has_writeable_rt =
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@ -572,16 +573,16 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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(color_writes & BITFIELD_BIT(i)) == 0;
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(color_writes & BITFIELD_BIT(i)) == 0;
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struct GENX(BLEND_STATE_ENTRY) entry = {
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struct GENX(BLEND_STATE_ENTRY) entry = {
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.WriteDisableAlpha = write_disabled ||
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.WriteDisableAlpha = write_disabled ||
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(pipeline->color_comp_writes[i] &
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(dyn->cb.attachments[i].write_mask &
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VK_COLOR_COMPONENT_A_BIT) == 0,
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VK_COLOR_COMPONENT_A_BIT) == 0,
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.WriteDisableRed = write_disabled ||
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.WriteDisableRed = write_disabled ||
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(pipeline->color_comp_writes[i] &
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(dyn->cb.attachments[i].write_mask &
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VK_COLOR_COMPONENT_R_BIT) == 0,
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VK_COLOR_COMPONENT_R_BIT) == 0,
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.WriteDisableGreen = write_disabled ||
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.WriteDisableGreen = write_disabled ||
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(pipeline->color_comp_writes[i] &
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(dyn->cb.attachments[i].write_mask &
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VK_COLOR_COMPONENT_G_BIT) == 0,
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VK_COLOR_COMPONENT_G_BIT) == 0,
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.WriteDisableBlue = write_disabled ||
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.WriteDisableBlue = write_disabled ||
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(pipeline->color_comp_writes[i] &
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(dyn->cb.attachments[i].write_mask &
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VK_COLOR_COMPONENT_B_BIT) == 0,
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VK_COLOR_COMPONENT_B_BIT) == 0,
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.LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],
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.LogicOpFunction = genX(vk_to_intel_logic_op)[dyn->cb.logic_op],
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.LogicOpEnable = dyn->cb.logic_op_enable,
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.LogicOpEnable = dyn->cb.logic_op_enable,
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