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Initial implementation of IF/ELSE/ENDIF using conditional masking.
mach->CondMask controls writing to each of the 4 components in a quad. mach->CondMaskStack handles nested conditionals. Only a few of the micro ops (add/sub/mul/store) have been updated to obey CondMask at this time.
This commit is contained in:
Brian
parent
ae7f200788
commit
fc38c82771
2 changed files with 124 additions and 191 deletions
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@ -96,6 +96,8 @@ tgsi_exec_machine_init(
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mach->Temps[TEMP_128_I].xyzw[TEMP_128_C].f[i] = 128.0f;
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mach->Temps[TEMP_M128_I].xyzw[TEMP_M128_C].f[i] = -128.0f;
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}
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mach->CondMask = 0xf;
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}
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void
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@ -175,12 +177,17 @@ static void
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micro_add(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1 )
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const union tgsi_exec_channel *src1,
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uint mask)
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{
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dst->f[0] = src0->f[0] + src1->f[0];
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dst->f[1] = src0->f[1] + src1->f[1];
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dst->f[2] = src0->f[2] + src1->f[2];
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dst->f[3] = src0->f[3] + src1->f[3];
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if (mask & 0x1)
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dst->f[0] = src0->f[0] + src1->f[0];
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if (mask & 0x2)
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dst->f[1] = src0->f[1] + src1->f[1];
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if (mask & 0x4)
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dst->f[2] = src0->f[2] + src1->f[2];
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if (mask & 0x8)
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dst->f[3] = src0->f[3] + src1->f[3];
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}
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static void
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@ -524,12 +531,17 @@ static void
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micro_mul(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1 )
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const union tgsi_exec_channel *src1,
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uint condMask)
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{
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dst->f[0] = src0->f[0] * src1->f[0];
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dst->f[1] = src0->f[1] * src1->f[1];
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dst->f[2] = src0->f[2] * src1->f[2];
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dst->f[3] = src0->f[3] * src1->f[3];
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if (condMask & 0x1)
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dst->f[0] = src0->f[0] * src1->f[0];
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if (condMask & 0x2)
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dst->f[1] = src0->f[1] * src1->f[1];
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if (condMask & 0x4)
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dst->f[2] = src0->f[2] * src1->f[2];
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if (condMask & 0x8)
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dst->f[3] = src0->f[3] * src1->f[3];
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}
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static void
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@ -720,12 +732,17 @@ static void
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micro_sub(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1 )
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const union tgsi_exec_channel *src1,
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uint mask)
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{
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dst->f[0] = src0->f[0] - src1->f[0];
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dst->f[1] = src0->f[1] - src1->f[1];
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dst->f[2] = src0->f[2] - src1->f[2];
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dst->f[3] = src0->f[3] - src1->f[3];
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if (mask & 0x1)
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dst->f[0] = src0->f[0] - src1->f[0];
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if (mask & 0x2)
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dst->f[1] = src0->f[1] - src1->f[1];
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if (mask & 0x4)
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dst->f[2] = src0->f[2] - src1->f[2];
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if (mask & 0x8)
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dst->f[3] = src0->f[3] - src1->f[3];
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}
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static void
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@ -940,7 +957,8 @@ store_dest(
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const union tgsi_exec_channel *chan,
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const struct tgsi_full_dst_register *reg,
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const struct tgsi_full_instruction *inst,
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GLuint chan_index )
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GLuint chan_index,
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uint mask)
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{
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union tgsi_exec_channel *dst;
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@ -968,7 +986,18 @@ store_dest(
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switch (inst->Instruction.Saturate)
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{
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case TGSI_SAT_NONE:
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#if 0
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*dst = *chan;
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#else
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if (mask & 0x1)
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dst->i[0] = chan->i[0];
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if (mask & 0x2)
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dst->i[1] = chan->i[1];
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if (mask & 0x4)
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dst->i[2] = chan->i[2];
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if (mask & 0x8)
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dst->i[3] = chan->i[3];
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#endif
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break;
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case TGSI_SAT_ZERO_ONE:
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@ -989,7 +1018,10 @@ store_dest(
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fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
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#define STORE(VAL,INDEX,CHAN)\
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN)
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN, ~0)
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#define STORE_MASKED(VAL,INDEX,CHAN,MASK) \
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN, MASK)
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static void
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exec_kil (struct tgsi_exec_machine *mach,
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@ -1113,6 +1145,7 @@ perspective_interpolation(
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}
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}
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typedef void (* interpolation_func)(
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struct tgsi_exec_machine *mach,
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unsigned attrib,
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@ -1209,7 +1242,7 @@ exec_instruction(
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/* TGSI_OPCODE_SWZ */
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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STORE( &r[0], 0, chan_index );
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STORE_MASKED( &r[0], 0, chan_index, mach->CondMask );
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}
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break;
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@ -1276,7 +1309,7 @@ exec_instruction(
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FETCH(&r[0], 0, chan_index);
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FETCH(&r[1], 1, chan_index);
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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STORE(&r[0], 0, chan_index);
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}
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@ -1286,7 +1319,7 @@ exec_instruction(
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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FETCH( &r[1], 1, chan_index );
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micro_add( &r[0], &r[0], &r[1] );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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STORE( &r[0], 0, chan_index );
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}
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break;
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@ -1295,17 +1328,17 @@ exec_instruction(
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/* TGSI_OPCODE_DOT3 */
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FETCH( &r[0], 0, CHAN_X );
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FETCH( &r[1], 1, CHAN_X );
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH( &r[1], 0, CHAN_Y );
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FETCH( &r[2], 1, CHAN_Y );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH( &r[1], 0, CHAN_Z );
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FETCH( &r[2], 1, CHAN_Z );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1317,25 +1350,25 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_X);
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FETCH(&r[1], 1, CHAN_X);
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 0, CHAN_Y);
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FETCH(&r[2], 1, CHAN_Y);
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 0, CHAN_Z);
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FETCH(&r[2], 1, CHAN_Z);
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 0, CHAN_W);
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FETCH(&r[2], 1, CHAN_W);
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1350,7 +1383,7 @@ exec_instruction(
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
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FETCH( &r[0], 0, CHAN_Y );
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FETCH( &r[1], 1, CHAN_Y);
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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STORE( &r[0], 0, CHAN_Y );
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}
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@ -1412,9 +1445,9 @@ exec_instruction(
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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FETCH( &r[1], 1, chan_index );
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH( &r[1], 2, chan_index );
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micro_add( &r[0], &r[0], &r[1] );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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STORE( &r[0], 0, chan_index );
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}
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break;
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@ -1424,7 +1457,7 @@ exec_instruction(
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FETCH(&r[0], 0, chan_index);
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FETCH(&r[1], 1, chan_index);
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micro_sub( &r[0], &r[0], &r[1] );
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micro_sub( &r[0], &r[0], &r[1], mach->CondMask );
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STORE(&r[0], 0, chan_index);
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}
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@ -1437,9 +1470,9 @@ exec_instruction(
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FETCH(&r[1], 1, chan_index);
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FETCH(&r[2], 2, chan_index);
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micro_sub( &r[1], &r[1], &r[2] );
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micro_mul( &r[0], &r[0], &r[1] );
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micro_add( &r[0], &r[0], &r[2] );
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micro_sub( &r[1], &r[1], &r[2], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_add( &r[0], &r[0], &r[2], mach->CondMask );
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STORE(&r[0], 0, chan_index);
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}
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@ -1533,13 +1566,13 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_Y);
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FETCH(&r[1], 1, CHAN_Z);
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micro_mul( &r[2], &r[0], &r[1] );
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micro_mul( &r[2], &r[0], &r[1], mach->CondMask );
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FETCH(&r[3], 0, CHAN_Z);
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FETCH(&r[4], 1, CHAN_Y);
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micro_mul( &r[5], &r[3], &r[4] );
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micro_sub( &r[2], &r[2], &r[5] );
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micro_mul( &r[5], &r[3], &r[4], mach->CondMask );
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micro_sub( &r[2], &r[2], &r[5], mach->CondMask );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
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STORE( &r[2], 0, CHAN_X );
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@ -1547,20 +1580,20 @@ exec_instruction(
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FETCH(&r[2], 1, CHAN_X);
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micro_mul( &r[3], &r[3], &r[2] );
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micro_mul( &r[3], &r[3], &r[2], mach->CondMask );
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FETCH(&r[5], 0, CHAN_X);
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micro_mul( &r[1], &r[1], &r[5] );
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micro_sub( &r[3], &r[3], &r[1] );
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micro_mul( &r[1], &r[1], &r[5], mach->CondMask );
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micro_sub( &r[3], &r[3], &r[1], mach->CondMask );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
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STORE( &r[3], 0, CHAN_Y );
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}
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micro_mul( &r[5], &r[5], &r[4] );
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micro_mul( &r[0], &r[0], &r[2] );
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micro_sub( &r[5], &r[5], &r[0] );
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micro_mul( &r[5], &r[5], &r[4], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[2], mach->CondMask );
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micro_sub( &r[5], &r[5], &r[0], mach->CondMask );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
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STORE( &r[5], 0, CHAN_Z );
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@ -1593,23 +1626,23 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_X);
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FETCH(&r[1], 1, CHAN_X);
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 0, CHAN_Y);
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FETCH(&r[2], 1, CHAN_Y);
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 0, CHAN_Z);
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FETCH(&r[2], 1, CHAN_Z);
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH(&r[1], 1, CHAN_W);
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micro_add( &r[0], &r[0], &r[1] );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1892,12 +1925,12 @@ exec_instruction(
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case TGSI_OPCODE_DP2:
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FETCH( &r[0], 0, CHAN_X );
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FETCH( &r[1], 1, CHAN_X );
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micro_mul( &r[0], &r[0], &r[1] );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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FETCH( &r[1], 0, CHAN_Y );
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FETCH( &r[2], 1, CHAN_Y );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1913,42 +1946,21 @@ exec_instruction(
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break;
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case TGSI_OPCODE_IF:
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{
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GLuint cond = 0;
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struct tgsi_exec_cond_state *state;
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/* Allocate condition state. */
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assert( mach->CondStack.Index > 0 );
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mach->CondStack.Index--;
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/* Evaluate the condition mask. */
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FETCH( &r[0], 0, CHAN_X );
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if( r[0].u[0] ) {
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cond |= 1;
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}
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if( r[0].u[1] ) {
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cond |= 2;
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}
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if( r[0].u[2] ) {
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cond |= 4;
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}
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if( r[0].u[3] ) {
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cond |= 8;
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}
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state = &mach->CondStack.States[mach->CondStack.Index];
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/* Initialize the If portion of condition state. */
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memcpy(
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state->IfPortion.TempsAddrs,
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mach->Temps,
|
||||
sizeof( state->IfPortion.TempsAddrs ) );
|
||||
memcpy(
|
||||
state->IfPortion.Outputs,
|
||||
mach->Outputs,
|
||||
sizeof( state->IfPortion.Outputs ) );
|
||||
state->Condition = cond;
|
||||
state->WasElse = GL_FALSE;
|
||||
/* push CondMask */
|
||||
mach->condStack[mach->CondStackTop++] = mach->CondMask;
|
||||
FETCH( &r[0], 0, CHAN_X );
|
||||
/* update CondMask */
|
||||
if( ! r[0].u[0] ) {
|
||||
mach->CondMask &= ~0x1;
|
||||
}
|
||||
if( ! r[0].u[1] ) {
|
||||
mach->CondMask &= ~0x2;
|
||||
}
|
||||
if( ! r[0].u[2] ) {
|
||||
mach->CondMask &= ~0x4;
|
||||
}
|
||||
if( ! r[0].u[3] ) {
|
||||
mach->CondMask &= ~0x8;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -1961,106 +1973,19 @@ exec_instruction(
|
|||
break;
|
||||
|
||||
case TGSI_OPCODE_ELSE:
|
||||
/* invert CondMask wrt previous mask */
|
||||
{
|
||||
struct tgsi_exec_cond_state *state;
|
||||
struct tgsi_exec_cond_regs temp;
|
||||
|
||||
state = &mach->CondStack.States[mach->CondStack.Index];
|
||||
|
||||
/* Copy the results of the If portion to temporary storage. */
|
||||
memcpy(
|
||||
temp.TempsAddrs,
|
||||
mach->Temps,
|
||||
sizeof( temp.TempsAddrs ) );
|
||||
memcpy(
|
||||
temp.Outputs,
|
||||
mach->Outputs,
|
||||
sizeof( temp.Outputs ) );
|
||||
|
||||
/* Restore the state of registers from before the If statement. */
|
||||
memcpy(
|
||||
mach->Temps,
|
||||
state->IfPortion.TempsAddrs,
|
||||
sizeof( state->IfPortion.TempsAddrs ) );
|
||||
memcpy(
|
||||
mach->Outputs,
|
||||
state->IfPortion.Outputs,
|
||||
sizeof( state->IfPortion.Outputs ) );
|
||||
|
||||
/* Save the results of If portion. */
|
||||
memcpy(
|
||||
&state->IfPortion,
|
||||
&temp,
|
||||
sizeof( state->IfPortion ) );
|
||||
state->WasElse = GL_TRUE;
|
||||
uint prevMask;
|
||||
assert(mach->CondStackTop > 0);
|
||||
prevMask = mach->condStack[mach->CondStackTop - 1];
|
||||
mach->CondMask = ~mach->CondMask & prevMask;
|
||||
}
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDIF:
|
||||
{
|
||||
struct tgsi_exec_cond_state *state;
|
||||
GLuint i;
|
||||
|
||||
state = &mach->CondStack.States[mach->CondStack.Index];
|
||||
|
||||
if( state->WasElse ) {
|
||||
/* Save the results of Else portion. */
|
||||
memcpy(
|
||||
state->ElsePortion.TempsAddrs,
|
||||
mach->Temps,
|
||||
sizeof( state->ElsePortion.TempsAddrs ) );
|
||||
memcpy(
|
||||
state->ElsePortion.Outputs,
|
||||
mach->Outputs,
|
||||
sizeof( state->ElsePortion.Outputs ) );
|
||||
}
|
||||
else {
|
||||
/* Copy the state of registers from before the If statement to Else portion. */
|
||||
memcpy(
|
||||
&state->ElsePortion,
|
||||
&state->IfPortion,
|
||||
sizeof( state->ElsePortion ) );
|
||||
|
||||
/* Save the results of the If portion. */
|
||||
memcpy(
|
||||
state->IfPortion.TempsAddrs,
|
||||
mach->Temps,
|
||||
sizeof( state->IfPortion.TempsAddrs ) );
|
||||
memcpy(
|
||||
state->IfPortion.Outputs,
|
||||
mach->Outputs,
|
||||
sizeof( state->IfPortion.Outputs ) );
|
||||
}
|
||||
|
||||
/* Mix the If and Else portions based on condition mask. */
|
||||
for( i = 0; i < 4; i++ ) {
|
||||
struct tgsi_exec_cond_regs *regs;
|
||||
GLuint j;
|
||||
|
||||
if( state->Condition & (1 << i) ) {
|
||||
regs = &state->IfPortion;
|
||||
}
|
||||
else {
|
||||
regs = &state->ElsePortion;
|
||||
}
|
||||
|
||||
for( j = 0; j < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_ADDRS; j++ ) {
|
||||
mach->Temps[j].xyzw[0].u[i] = regs->TempsAddrs[j].xyzw[0].u[i];
|
||||
mach->Temps[j].xyzw[1].u[i] = regs->TempsAddrs[j].xyzw[1].u[i];
|
||||
mach->Temps[j].xyzw[2].u[i] = regs->TempsAddrs[j].xyzw[2].u[i];
|
||||
mach->Temps[j].xyzw[3].u[i] = regs->TempsAddrs[j].xyzw[3].u[i];
|
||||
}
|
||||
for( j = 0; j < 2; j++ ) {
|
||||
mach->Outputs[j].xyzw[0].u[i] = regs->Outputs[j].xyzw[0].u[i];
|
||||
mach->Outputs[j].xyzw[1].u[i] = regs->Outputs[j].xyzw[1].u[i];
|
||||
mach->Outputs[j].xyzw[2].u[i] = regs->Outputs[j].xyzw[2].u[i];
|
||||
mach->Outputs[j].xyzw[3].u[i] = regs->Outputs[j].xyzw[3].u[i];
|
||||
}
|
||||
}
|
||||
|
||||
/* Release condition state. */
|
||||
mach->CondStack.Index++;
|
||||
}
|
||||
assert(mach->CondStackTop > 0);
|
||||
/* pop CondMask */
|
||||
mach->CondMask = mach->condStack[--mach->CondStackTop];
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDLOOP:
|
||||
|
|
@ -2247,8 +2172,6 @@ tgsi_exec_machine_run2(
|
|||
mach->Primitives[0] = 0;
|
||||
}
|
||||
|
||||
mach->CondStack.Index = 8;
|
||||
|
||||
k = tgsi_parse_init( &parse, mach->Tokens );
|
||||
if (k != TGSI_PARSE_OK) {
|
||||
printf("Problem parsing!\n");
|
||||
|
|
|
|||
|
|
@ -120,6 +120,10 @@ struct tgsi_exec_cond_stack
|
|||
unsigned Index; /* into States[] */
|
||||
};
|
||||
|
||||
|
||||
#define TGSI_EXEC_MAX_COND_NESTING 10
|
||||
|
||||
|
||||
struct tgsi_exec_machine
|
||||
{
|
||||
/*
|
||||
|
|
@ -152,9 +156,15 @@ struct tgsi_exec_machine
|
|||
/* FRAGMENT processor only. */
|
||||
const struct tgsi_interp_coef *InterpCoefs;
|
||||
|
||||
struct tgsi_exec_cond_stack CondStack;
|
||||
/* Conditional execution mask */
|
||||
uint CondMask;
|
||||
|
||||
/* Condition mask stack (for nested conditionals) */
|
||||
uint condStack[TGSI_EXEC_MAX_COND_NESTING];
|
||||
int CondStackTop;
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
tgsi_exec_machine_init(
|
||||
struct tgsi_exec_machine *mach,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue