From fc02ffed248847e544f3f6700a104dd732711a9a Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 10 Jun 2026 15:29:47 +0100 Subject: [PATCH] radv: merge radv_shader_stage_key for combined ahit/isec shaders This should be done if the any-hit enables robustness but the intersection does not. Signed-off-by: Rhys Perry Reviewed-by: Konstantin Seurer Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline.c | 25 +++++++++++++++++++++++++ src/amd/vulkan/radv_pipeline.h | 2 ++ src/amd/vulkan/radv_pipeline_rt.c | 3 +++ 3 files changed, 30 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4ffadb0c953..cbb6ece5ed1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -168,6 +168,31 @@ radv_pipeline_get_shader_key(const struct radv_compiler_info *compiler_info, return key; } +void +radv_merge_shader_stage_key(struct radv_shader_stage_key *dst, const struct radv_shader_stage_key *src) +{ + assert(dst->subgroup_required_size == src->subgroup_required_size); + assert(dst->view_index_from_device_index == src->view_index_from_device_index); + assert(dst->descriptor_heap == src->descriptor_heap); + assert(dst->version == src->version); + assert(dst->has_task_shader == src->has_task_shader); + + dst->subgroup_require_full |= src->subgroup_require_full; + dst->subgroup_allow_varying &= src->subgroup_allow_varying; + + dst->storage_robustness2 |= src->storage_robustness2; + dst->uniform_robustness2 |= src->uniform_robustness2; + dst->vertex_robustness1 |= src->vertex_robustness1; + dst->coop_matrix_storage_robustness |= src->coop_matrix_storage_robustness; + dst->coop_matrix_uniform_robustness |= src->coop_matrix_uniform_robustness; + + dst->optimisations_disabled |= src->optimisations_disabled; + dst->keep_statistic_info |= src->keep_statistic_info; + dst->keep_executable_info |= src->keep_executable_info; + dst->keep_shader_arg_info |= src->keep_shader_arg_info; + dst->indirect_bindable |= src->indirect_bindable; +} + void radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPipelineShaderStageCreateInfo *sinfo, const struct radv_pipeline_layout *pipeline_layout, diff --git a/src/amd/vulkan/radv_pipeline.h b/src/amd/vulkan/radv_pipeline.h index 1694650341f..8865b483bf6 100644 --- a/src/amd/vulkan/radv_pipeline.h +++ b/src/amd/vulkan/radv_pipeline.h @@ -86,6 +86,8 @@ struct radv_shader_stage_key radv_pipeline_get_shader_key(const struct radv_comp const VkPipelineShaderStageCreateInfo *stage, VkPipelineCreateFlags2 flags, const void *pNext); +void radv_merge_shader_stage_key(struct radv_shader_stage_key *dst, const struct radv_shader_stage_key *src); + void radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPipelineShaderStageCreateInfo *sinfo, const struct radv_pipeline_layout *layout, const struct radv_shader_stage_key *stage_key, struct radv_shader_stage *out_stage); diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index bbecc8fe3fe..24a4b90895d 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -860,7 +860,10 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca .nir = final_shader, .key = rt_stages[isec ? isec_idx : ahit_idx].key, }; + if (isec && ahit) + radv_merge_shader_stage_key(&combined_stage.key, &rt_stages[ahit_idx].key); radv_shader_layout_init(pipeline_layout, final_shader->info.stage, &combined_stage.layout); + uint32_t stack_size = 0; struct radv_serialized_shader_arena_block *replay_block = capture_replay_handles[idx].arena_va ? &capture_replay_handles[idx] : NULL;