From fb9de08efdf68a4458fb40bbc032bf94a80108ef Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Wed, 22 Jan 2025 15:33:47 +0100 Subject: [PATCH] ir3/a7xx: document alias.rt It works completely differently from alias.tex. Signed-off-by: Job Noorman Part-of: --- src/freedreno/isa/ir3-cat7.xml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/freedreno/isa/ir3-cat7.xml b/src/freedreno/isa/ir3-cat7.xml index 73acfd29842..1d701a2214c 100644 --- a/src/freedreno/isa/ir3-cat7.xml +++ b/src/freedreno/isa/ir3-cat7.xml @@ -298,6 +298,8 @@ SOFTWARE. + For alias.tex (and possibly alias.mem): + Add an entry to the scope-specific "alias table", when instruction from that scope tries to access a source register it would search its alias table first. @@ -322,6 +324,20 @@ SOFTWARE. In this case, the size of the table is bounded (max 16 entries) and the number of entries in the table is indicated by the first alias instruction in the TABLE_SIZE_MINUS_ONE field. + + For alias.rt: create an entry into the alias table for a render + target. For example, this would map the 4th component of render + target 0 (FRAG_RESULT_DATA0) to the constant 0x0: + alias.rt.b32.0 rt0.w, (0x0) + + alias.rt has to be executed in the preamble and can only map + const registers and immediates. Additionally, the register + SP_PS_ALIASED_COMPONENTS has to be set to a mask of render + target components that will be aliased. + + In this case, the size of the table is only bounded by the + number of render targets/components and the TABLE_SIZE_MINUS_ONE + field is not used.