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ir3: memory_barrier also controls shared memory access order

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nir_intrinsic_memory_barrier has the same semantic as memoryBarrier()
in GLSL, which is:

GLSL 4.60, 4.10. "Memory Qualifiers":
 "The built-in function memoryBarrier() can be used if needed to
 guarantee the completion and relative ordering of memory accesses
 performed by a single shader invocation."

GLSL 4.60, 8.17. "Shader Memory Control Functions":
 "The built-in functions memoryBarrier() and groupMemoryBarrier() wait
 for the completion of accesses to all of the above variable types."

Fixes tests:
 dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp
 dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp

Fixes: 819a613a ("freedreno/ir3: moar better scheduler")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
(cherry picked from commit cb8a00791c)
This commit is contained in:
Danylo Piliaiev 2021-02-15 15:53:46 +02:00 • committed by Eric Engestrom
parent ceafcf3daf
commit fb696bbbe2
4 changed files with 3 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -211,7 +211,7 @@
"description": "ir3: memory_barrier also controls shared memory access order",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "819a613ae33410584e13e78e78af82c71716f67d"
},

2
src/freedreno/ci/deqp-freedreno-a630-fails.txt
View file

@ -129,8 +129,6 @@ dEQP-VK.image.subresource_layout.3d.all_levels.r16g16b16a16_snorm,Fail
dEQP-VK.image.subresource_layout.3d.all_levels.r8_snorm,Fail
dEQP-VK.image.subresource_layout.3d.all_levels.r8g8b8a8_snorm,Fail
dEQP-VK.info.device_mandatory_features,Fail
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp,Fail
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp,Fail
dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_always_greater,Fail
dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_greater,Fail
dEQP-VK.pipeline.extended_dynamic_state.after_pipelines.depth_compare_greater_equal_greater,Fail

2
src/freedreno/ir3/ir3.h
View file

@ -392,7 +392,7 @@ struct ir3_instruction {
* shared image atomic SSBO everything
* barrier()/ - R/W R/W R/W R/W X
* groupMemoryBarrier()
* memoryBarrier() - R/W R/W
* memoryBarrier()
* (but only images declared coherent?)
* memoryBarrierAtomic() - R/W
* memoryBarrierBuffer() - R/W

13
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -1312,18 +1312,6 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
barrier->barrier_class = IR3_BARRIER_EVERYTHING;
break;
case nir_intrinsic_memory_barrier:
barrier = ir3_FENCE(b);
barrier->cat7.g = true;
barrier->cat7.r = true;
barrier->cat7.w = true;
barrier->cat7.l = true;
barrier->barrier_class = IR3_BARRIER_IMAGE_W |
IR3_BARRIER_BUFFER_W;
barrier->barrier_conflict =
IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
break;
case nir_intrinsic_memory_barrier_buffer:
barrier = ir3_FENCE(b);
barrier->cat7.g = true;
@ -1353,6 +1341,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
IR3_BARRIER_SHARED_W;
break;
case nir_intrinsic_memory_barrier:
case nir_intrinsic_group_memory_barrier:
barrier = ir3_FENCE(b);
barrier->cat7.g = true;