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nir: add shader_info::tess::tcs_same_invocation_inputs_read(_indirect)

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We need both the same-invocation usage mask and cross-invocation usage
mask. The AMD reason is below.

Cross-invocation TCS input access doesn't prevent the same-invocation
fast path in AMD hw because it's just a different way to load the same
data, and we want to use both paths for the same TCS input based on
the load instruction. The fast path can't be used for indirect access,
which is gathered separately for same-invocation access.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31645>
This commit is contained in:
Marek Olšák 2024-10-01 16:05:12 -04:00 • committed by Marge Bot
parent 9ef6ff1702
commit fb6184f89c
3 changed files with 23 additions and 5 deletions
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18
src/compiler/nir/nir_gather_info.c
View file

@ -147,8 +147,12 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
shader->info.inputs_read_indirectly |= bitfield;
}
if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
shader->info.tess.tcs_cross_invocation_inputs_read |= bitfield;
if (shader->info.stage == MESA_SHADER_TESS_CTRL) {
if (cross_invocation)
shader->info.tess.tcs_cross_invocation_inputs_read |= bitfield;
else
shader->info.tess.tcs_same_invocation_inputs_read |= bitfield;
}
if (shader->info.stage == MESA_SHADER_FRAGMENT) {
shader->info.fs.uses_sample_qualifier |= var->data.sample;
@ -564,9 +568,12 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
}
if (shader->info.stage == MESA_SHADER_TESS_CTRL &&
instr->intrinsic == nir_intrinsic_load_per_vertex_input &&
!src_is_invocation_id(nir_get_io_arrayed_index_src(instr)))
shader->info.tess.tcs_cross_invocation_inputs_read |= slot_mask;
instr->intrinsic == nir_intrinsic_load_per_vertex_input) {
if (src_is_invocation_id(nir_get_io_arrayed_index_src(instr)))
shader->info.tess.tcs_same_invocation_inputs_read |= slot_mask;
else
shader->info.tess.tcs_cross_invocation_inputs_read |= slot_mask;
}
break;
case nir_intrinsic_load_output:
@ -1022,6 +1029,7 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.fs.needs_quad_helper_invocations = false;
}
if (shader->info.stage == MESA_SHADER_TESS_CTRL) {
shader->info.tess.tcs_same_invocation_inputs_read = 0;
shader->info.tess.tcs_cross_invocation_inputs_read = 0;
shader->info.tess.tcs_cross_invocation_outputs_read = 0;
}

2
src/compiler/nir/nir_print.c
View file

@ -2587,6 +2587,8 @@ print_shader_info(const struct shader_info *info, FILE *fp)
print_nz_bool(fp, "ccw", info->tess.ccw);
print_nz_bool(fp, "point_mode", info->tess.point_mode);
print_nz_x64(fp, "tcs_same_invocation_inputs_read",
info->tess.tcs_same_invocation_inputs_read);
print_nz_x64(fp, "tcs_cross_invocation_inputs_read", info->tess.tcs_cross_invocation_inputs_read);
print_nz_x64(fp, "tcs_cross_invocation_outputs_read", info->tess.tcs_cross_invocation_outputs_read);
break;

8
src/compiler/shader_info.h
View file

@ -490,6 +490,14 @@ typedef struct shader_info {
bool ccw:1;
bool point_mode:1;
/* Bit mask of TCS per-vertex inputs (VS outputs) that are used
* with a vertex index that is equal to the invocation id.
*
* Not mutually exclusive with tcs_cross_invocation_inputs_read, i.e.
* both input[0] and input[invocation_id] can be present.
*/
uint64_t tcs_same_invocation_inputs_read;
/* Bit mask of TCS per-vertex inputs (VS outputs) that are used
* with a vertex index that is NOT the invocation id
*/