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i965: add SHADER_OPCODE_TG4

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Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().

V3: Updated for changes in master.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Chris Forbes 2013-03-31 21:31:12 +13:00
parent 18002d9eda
commit fb455500bf
6 changed files with 17 additions and 2 deletions
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3
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -767,6 +767,7 @@ enum opcode {
FS_OPCODE_TXB,
SHADER_OPCODE_TXF_MS,
SHADER_OPCODE_LOD,
SHADER_OPCODE_TG4,
SHADER_OPCODE_SHADER_TIME_ADD,
@ -1042,8 +1043,10 @@ enum brw_message_target {
#define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
#define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
#define GEN5_SAMPLER_MESSAGE_LOD 9
#define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
#define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
#define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
#define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30

1
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -725,6 +725,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:

5
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -431,6 +431,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
case SHADER_OPCODE_LOD:
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
break;
case SHADER_OPCODE_TG4:
assert(brw->gen >= 6);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
default:
assert(!"not reached");
break;
@ -1403,6 +1407,7 @@ fs_generator::generate_code(exec_list *instructions)
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
generate_tex(inst, dst, src[0]);
break;
case FS_OPCODE_DDX:

3
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -532,7 +532,8 @@ backend_instruction::is_tex()
opcode == SHADER_OPCODE_TXF_MS ||
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD);
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4);
}
bool

1
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -270,6 +270,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
return inst->header_present ? 1 : 0;
default:
assert(!"not reached");

6
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -308,6 +308,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TXS:
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
case SHADER_OPCODE_TG4:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
default:
assert(!"should not get here: invalid VS texture opcode");
break;
@ -361,7 +364,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
brw_MOV(p,
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
BRW_REGISTER_TYPE_UD),
brw_imm_uw(inst->texture_offset));
brw_imm_ud(inst->texture_offset));
brw_pop_insn_state(p);
} else if (inst->header_present) {
/* Set up an implied move from g0 to the MRF. */
@ -1040,6 +1043,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
generate_tex(inst, dst, src[0]);
break;