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radv: use intrinsic builders

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
This commit is contained in:
Rhys Perry 2020-09-03 19:44:00 +01:00 • committed by Marge Bot
parent 9b040737d3
commit fb0385b57c
11 changed files with 183 additions and 643 deletions
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25
src/amd/vulkan/radv_meta.c
View file

@ -505,9 +505,7 @@ radv_device_finish_meta(struct radv_device *device)
nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2)
{
nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(vs_b->shader, nir_intrinsic_load_vertex_id_zero_base);
nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
nir_builder_instr_insert(vs_b, &vertex_id->instr);
nir_ssa_def *vertex_id = nir_load_vertex_id_zero_base(vs_b);
/* vertex 0 - -1.0, -1.0 */
/* vertex 1 - -1.0, 1.0 */
@ -515,10 +513,8 @@ nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *c
/* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
channel 1 is vertex id != 1 ? -1.0 : 1.0 */
nir_ssa_def *c0cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
nir_imm_int(vs_b, 2));
nir_ssa_def *c1cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
nir_imm_int(vs_b, 1));
nir_ssa_def *c0cmp = nir_ine(vs_b, vertex_id, nir_imm_int(vs_b, 2));
nir_ssa_def *c1cmp = nir_ine(vs_b, vertex_id, nir_imm_int(vs_b, 1));
nir_ssa_def *comp[4];
comp[0] = nir_bcsel(vs_b, c0cmp,
@ -651,16 +647,7 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
nir_ssa_def *
radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
{
nir_intrinsic_instr *rsrc =
nir_intrinsic_instr_create(b->shader,
nir_intrinsic_vulkan_resource_index);
rsrc->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
rsrc->num_components = 2;
nir_intrinsic_set_desc_set(rsrc, desc_set);
nir_intrinsic_set_binding(rsrc, binding);
nir_ssa_dest_init(&rsrc->instr, &rsrc->dest, rsrc->num_components, 32, NULL);
nir_builder_instr_insert(b, &rsrc->instr);
return nir_channel(b, &rsrc->dest.ssa, 0);
nir_ssa_def *rsrc = nir_vulkan_resource_index(
b, 2, 32, nir_imm_int(b, 0), .desc_set=desc_set, .binding=binding);
return nir_channel(b, rsrc, 0);
}

37
src/amd/vulkan/radv_meta_blit.c
View file

@ -57,25 +57,10 @@ build_nir_vertex_shader(void)
nir_store_var(&b, pos_out, outvec, 0xf);
nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_intrinsic_set_base(src_box, 0);
nir_intrinsic_set_range(src_box, 16);
src_box->num_components = 4;
nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
nir_builder_instr_insert(&b, &src_box->instr);
nir_ssa_def *src_box = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *src0_z = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .base=16, .range=4);
nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_intrinsic_set_base(src0_z, 16);
nir_intrinsic_set_range(src0_z, 4);
src0_z->num_components = 1;
nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
nir_builder_instr_insert(&b, &src0_z->instr);
nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
nir_builder_instr_insert(&b, &vertex_id->instr);
nir_ssa_def *vertex_id = nir_load_vertex_id_zero_base(&b);
/* vertex 0 - src0_x, src0_y, src0_z */
/* vertex 1 - src0_x, src1_y, src0_z*/
@ -83,20 +68,18 @@ build_nir_vertex_shader(void)
/* so channel 0 is vertex_id != 2 ? src_x : src_x + w
channel 1 is vertex id != 1 ? src_y : src_y + w */
nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
nir_imm_int(&b, 2));
nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
nir_imm_int(&b, 1));
nir_ssa_def *c0cmp = nir_ine(&b, vertex_id, nir_imm_int(&b, 2));
nir_ssa_def *c1cmp = nir_ine(&b, vertex_id, nir_imm_int(&b, 1));
nir_ssa_def *comp[4];
comp[0] = nir_bcsel(&b, c0cmp,
nir_channel(&b, &src_box->dest.ssa, 0),
nir_channel(&b, &src_box->dest.ssa, 2));
nir_channel(&b, src_box, 0),
nir_channel(&b, src_box, 2));
comp[1] = nir_bcsel(&b, c1cmp,
nir_channel(&b, &src_box->dest.ssa, 1),
nir_channel(&b, &src_box->dest.ssa, 3));
comp[2] = &src0_z->dest.ssa;
nir_channel(&b, src_box, 1),
nir_channel(&b, src_box, 3));
comp[2] = src0_z;
comp[3] = nir_imm_float(&b, 1.0);
nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);

53
src/amd/vulkan/radv_meta_blit2d.c
View file

@ -442,17 +442,8 @@ build_nir_vertex_shader(void)
nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
nir_store_var(&b, pos_out, outvec, 0xf);
nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_intrinsic_set_base(src_box, 0);
nir_intrinsic_set_range(src_box, 16);
src_box->num_components = 4;
nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
nir_builder_instr_insert(&b, &src_box->instr);
nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
nir_builder_instr_insert(&b, &vertex_id->instr);
nir_ssa_def *src_box = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *vertex_id = nir_load_vertex_id_zero_base(&b);
/* vertex 0 - src_x, src_y */
/* vertex 1 - src_x, src_y+h */
@ -460,19 +451,19 @@ build_nir_vertex_shader(void)
/* so channel 0 is vertex_id != 2 ? src_x : src_x + w
channel 1 is vertex id != 1 ? src_y : src_y + w */
nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
nir_ssa_def *c0cmp = nir_ine(&b, vertex_id,
nir_imm_int(&b, 2));
nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
nir_ssa_def *c1cmp = nir_ine(&b, vertex_id,
nir_imm_int(&b, 1));
nir_ssa_def *comp[2];
comp[0] = nir_bcsel(&b, c0cmp,
nir_channel(&b, &src_box->dest.ssa, 0),
nir_channel(&b, &src_box->dest.ssa, 2));
nir_channel(&b, src_box, 0),
nir_channel(&b, src_box, 2));
comp[1] = nir_bcsel(&b, c1cmp,
nir_channel(&b, &src_box->dest.ssa, 1),
nir_channel(&b, &src_box->dest.ssa, 3));
nir_channel(&b, src_box, 1),
nir_channel(&b, src_box, 3));
nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 2);
nir_store_var(&b, tex_pos_out, out_tex_vec, 0x3);
return b.shader;
@ -496,26 +487,18 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
sampler->data.binding = 0;
nir_ssa_def *tex_pos_3d = NULL;
nir_intrinsic_instr *sample_idx = NULL;
nir_ssa_def *sample_idx = NULL;
if (is_3d) {
nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(layer, 16);
nir_intrinsic_set_range(layer, 4);
layer->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
layer->num_components = 1;
nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
nir_builder_instr_insert(b, &layer->instr);
nir_ssa_def *layer = nir_load_push_constant(b, 1, 32, nir_imm_int(b, 0), .base=16, .range=4);
nir_ssa_def *chans[3];
chans[0] = nir_channel(b, tex_pos, 0);
chans[1] = nir_channel(b, tex_pos, 1);
chans[2] = &layer->dest.ssa;
chans[2] = layer;
tex_pos_3d = nir_vec(b, chans, 3);
}
if (is_multisampled) {
sample_idx = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_sample_id);
nir_ssa_dest_init(&sample_idx->instr, &sample_idx->dest, 1, 32, "sample_idx");
nir_builder_instr_insert(b, &sample_idx->instr);
sample_idx = nir_load_sample_id(b);
}
nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;
@ -526,7 +509,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
tex->src[0].src_type = nir_tex_src_coord;
tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
tex->src[1].src_type = is_multisampled ? nir_tex_src_ms_index : nir_tex_src_lod;
tex->src[1].src = nir_src_for_ssa(is_multisampled ? &sample_idx->dest.ssa : nir_imm_int(b, 0));
tex->src[1].src = nir_src_for_ssa(is_multisampled ? sample_idx : nir_imm_int(b, 0));
tex->src[2].src_type = nir_tex_src_texture_deref;
tex->src[2].src = nir_src_for_ssa(tex_deref);
if (is_multisampled) {
@ -555,17 +538,11 @@ build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
sampler->data.descriptor_set = 0;
sampler->data.binding = 0;
nir_intrinsic_instr *width = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(width, 16);
nir_intrinsic_set_range(width, 4);
width->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
width->num_components = 1;
nir_ssa_dest_init(&width->instr, &width->dest, 1, 32, "width");
nir_builder_instr_insert(b, &width->instr);
nir_ssa_def *width = nir_load_push_constant(b, 1, 32, nir_imm_int(b, 0), .base=16, .range=4);
nir_ssa_def *pos_x = nir_channel(b, tex_pos, 0);
nir_ssa_def *pos_y = nir_channel(b, tex_pos, 1);
pos_y = nir_imul(b, pos_y, &width->dest.ssa);
pos_y = nir_imul(b, pos_y, width);
pos_x = nir_iadd(b, pos_x, pos_y);
nir_ssa_def *tex_deref = &nir_build_deref_var(b, sampler)->dest.ssa;

42
src/amd/vulkan/radv_meta_buffer.c
View file

@ -27,25 +27,11 @@ build_buffer_fill_shader(struct radv_device *dev)
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(load, 0);
nir_intrinsic_set_range(load, 4);
load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
load->num_components = 1;
nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, "fill_value");
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *load = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range=4);
nir_ssa_def *swizzled_load = nir_swizzle(&b, load, (unsigned[]) { 0, 0, 0, 0}, 4);
nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(swizzled_load);
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
nir_intrinsic_set_align(store, 16, 0);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, swizzled_load, dst_buf, offset, .write_mask=0xf,
.access=ACCESS_NON_READABLE, .align_mul=16);
return b.shader;
}
@ -74,23 +60,9 @@ build_buffer_copy_shader(struct radv_device *dev)
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(offset);
nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
load->num_components = 4;
nir_intrinsic_set_align(load, 16, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(&load->dest.ssa);
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
nir_intrinsic_set_align(store, 16, 0);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);
nir_ssa_def *load = nir_load_ssbo(&b, 4, 32, src_buf, offset, .align_mul=16);
nir_store_ssbo(&b, load, dst_buf, offset, .write_mask=0xf,
.access=ACCESS_NON_READABLE, .align_mul=16);
return b.shader;
}

238
src/amd/vulkan/radv_meta_bufimage.c
View file

@ -66,25 +66,10 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_ssa_def *offset = nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range=16);
nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(offset, 0);
nir_intrinsic_set_range(offset, 16);
offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
offset->num_components = is_3d ? 3 : 2;
nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset");
nir_builder_instr_insert(&b, &offset->instr);
nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(stride, 0);
nir_intrinsic_set_range(stride, 16);
stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
stride->num_components = 1;
nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
nir_builder_instr_insert(&b, &stride->instr);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, offset);
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
@ -106,21 +91,15 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *pos_x = nir_channel(&b, global_id, 0);
nir_ssa_def *pos_y = nir_channel(&b, global_id, 1);
nir_ssa_def *tmp = nir_imul(&b, pos_y, &stride->dest.ssa);
nir_ssa_def *tmp = nir_imul(&b, pos_y, stride);
tmp = nir_iadd(&b, tmp, pos_x);
nir_ssa_def *coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
nir_ssa_def *outval = &tex->dest.ssa;
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
return b.shader;
}
@ -293,31 +272,18 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(offset, 0);
nir_intrinsic_set_range(offset, 16);
offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
offset->num_components = is_3d ? 3 : 2;
nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset");
nir_builder_instr_insert(&b, &offset->instr);
nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(stride, 0);
nir_intrinsic_set_range(stride, 16);
stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
stride->num_components = 1;
nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
nir_builder_instr_insert(&b, &stride->instr);
nir_ssa_def *offset = nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range=16);
nir_ssa_def *pos_x = nir_channel(&b, global_id, 0);
nir_ssa_def *pos_y = nir_channel(&b, global_id, 1);
nir_ssa_def *tmp = nir_imul(&b, pos_y, &stride->dest.ssa);
nir_ssa_def *tmp = nir_imul(&b, pos_y, stride);
tmp = nir_iadd(&b, tmp, pos_x);
nir_ssa_def *buf_coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, offset);
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
@ -337,15 +303,9 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
nir_builder_instr_insert(&b, &tex->instr);
nir_ssa_def *outval = &tex->dest.ssa;
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(img_coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
img_coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
return b.shader;
}
@ -513,43 +473,23 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(offset, 0);
nir_intrinsic_set_range(offset, 16);
offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
offset->num_components = 2;
nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset");
nir_builder_instr_insert(&b, &offset->instr);
nir_intrinsic_instr *pitch = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(pitch, 0);
nir_intrinsic_set_range(pitch, 16);
pitch->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
pitch->num_components = 1;
nir_ssa_dest_init(&pitch->instr, &pitch->dest, 1, 32, "pitch");
nir_builder_instr_insert(&b, &pitch->instr);
nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(stride, 0);
nir_intrinsic_set_range(stride, 16);
stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
stride->num_components = 1;
nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
nir_builder_instr_insert(&b, &stride->instr);
nir_ssa_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *pitch = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range=16);
nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range=16);
nir_ssa_def *pos_x = nir_channel(&b, global_id, 0);
nir_ssa_def *pos_y = nir_channel(&b, global_id, 1);
nir_ssa_def *tmp = nir_imul(&b, pos_y, &stride->dest.ssa);
nir_ssa_def *tmp = nir_imul(&b, pos_y, stride);
tmp = nir_iadd(&b, tmp, pos_x);
nir_ssa_def *buf_coord = nir_vec4(&b, tmp, tmp, tmp, tmp);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa);
nir_ssa_def *img_coord = nir_iadd(&b, global_id, offset);
nir_ssa_def *global_pos =
nir_iadd(&b,
nir_imul(&b, nir_channel(&b, img_coord, 1), &pitch->dest.ssa),
nir_imul(&b, nir_channel(&b, img_coord, 1), pitch),
nir_imul(&b, nir_channel(&b, img_coord, 0), nir_imm_int(&b, 3)));
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
@ -575,17 +515,12 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_ssa_def *local_pos =
nir_iadd(&b, global_pos, nir_imm_int(&b, chan));
nir_ssa_def *coord =
nir_ssa_def *coord =
nir_vec4(&b, local_pos, local_pos, local_pos, local_pos);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 1;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(nir_channel(&b, outval, chan));
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
coord, nir_ssa_undef(&b, 1, 32),
nir_channel(&b, outval, chan), nir_imm_int(&b, 0));
}
return b.shader;
@ -719,26 +654,13 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 24);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = is_3d ? 3 : 2;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, is_3d ? 3 : 2, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 0), .range=24);
nir_ssa_def *dst_offset = nir_load_push_constant(&b, is_3d ? 3 : 2, 32, nir_imm_int(&b, 12), .range=24);
nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(dst_offset, 0);
nir_intrinsic_set_range(dst_offset, 24);
dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
dst_offset->num_components = is_3d ? 3 : 2;
nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, is_3d ? 3 : 2, 32, "dst_offset");
nir_builder_instr_insert(&b, &dst_offset->instr);
nir_ssa_def *src_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa);
nir_ssa_def *src_coord = nir_iadd(&b, global_id, src_offset);
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
nir_ssa_def *dst_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
nir_ssa_def *dst_coord = nir_iadd(&b, global_id, dst_offset);
nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
tex->sampler_dim = dim;
@ -757,15 +679,9 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d)
nir_builder_instr_insert(&b, &tex->instr);
nir_ssa_def *outval = &tex->dest.ssa;
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(dst_coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
dst_coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
return b.shader;
}
@ -934,28 +850,14 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 24);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = 3;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 3, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range=24);
nir_ssa_def *dst_offset = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 12), .range=24);
nir_ssa_def *src_stride = nir_channel(&b, &src_offset->dest.ssa, 2);
nir_ssa_def *src_stride = nir_channel(&b, src_offset, 2);
nir_ssa_def *dst_stride = nir_channel(&b, dst_offset, 2);
nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(dst_offset, 0);
nir_intrinsic_set_range(dst_offset, 24);
dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
dst_offset->num_components = 3;
nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 3, 32, "dst_offset");
nir_builder_instr_insert(&b, &dst_offset->instr);
nir_ssa_def *dst_stride = nir_channel(&b, &dst_offset->dest.ssa, 2);
nir_ssa_def *src_img_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa);
nir_ssa_def *dst_img_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
nir_ssa_def *src_img_coord = nir_iadd(&b, global_id, src_offset);
nir_ssa_def *dst_img_coord = nir_iadd(&b, global_id, dst_offset);
nir_ssa_def *src_global_pos =
nir_iadd(&b,
@ -1003,16 +905,9 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_vec4(&b, dst_local_pos, dst_local_pos,
dst_local_pos, dst_local_pos);
nir_intrinsic_instr *store =
nir_intrinsic_instr_create(b.shader,
nir_intrinsic_image_deref_store);
store->num_components = 1;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(dst_coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(nir_channel(&b, outval, 0));
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
dst_coord, nir_ssa_undef(&b, 1, 32),
nir_channel(&b, outval, 0), nir_imm_int(&b, 0));
}
return b.shader;
@ -1139,23 +1034,10 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(clear_val, 0);
nir_intrinsic_set_range(clear_val, 20);
clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
clear_val->num_components = 4;
nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value");
nir_builder_instr_insert(&b, &clear_val->instr);
nir_ssa_def *clear_val = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 0), .range=20);
nir_ssa_def *layer = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 16), .range=20);
nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(layer, 0);
nir_intrinsic_set_range(layer, 20);
layer->src[0] = nir_src_for_ssa(nir_imm_int(&b, 16));
layer->num_components = 1;
nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
nir_builder_instr_insert(&b, &layer->instr);
nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), &layer->dest.ssa);
nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), layer);
nir_ssa_def *comps[4];
comps[0] = nir_channel(&b, global_id, 0);
@ -1164,15 +1046,9 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d)
comps[3] = nir_imm_int(&b, 0);
global_id = nir_vec(&b, comps, 4);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(global_id);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(&clear_val->dest.ssa);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
global_id, nir_ssa_undef(&b, 1, 32), clear_val, nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
return b.shader;
}
@ -1329,28 +1205,15 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(clear_val, 0);
nir_intrinsic_set_range(clear_val, 16);
clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
clear_val->num_components = 3;
nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 3, 32, "clear_value");
nir_builder_instr_insert(&b, &clear_val->instr);
nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(stride, 0);
nir_intrinsic_set_range(stride, 16);
stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12));
stride->num_components = 1;
nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride");
nir_builder_instr_insert(&b, &stride->instr);
nir_ssa_def *clear_val = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range=16);
nir_ssa_def *global_x = nir_channel(&b, global_id, 0);
nir_ssa_def *global_y = nir_channel(&b, global_id, 1);
nir_ssa_def *global_pos =
nir_iadd(&b,
nir_imul(&b, global_y, &stride->dest.ssa),
nir_imul(&b, global_y, stride),
nir_imul(&b, global_x, nir_imm_int(&b, 3)));
for (unsigned chan = 0; chan < 3; chan++) {
@ -1360,14 +1223,9 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
nir_ssa_def *coord =
nir_vec4(&b, local_pos, local_pos, local_pos, local_pos);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 1;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(nir_channel(&b, &clear_val->dest.ssa, chan));
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
coord, nir_ssa_undef(&b, 1, 32),
nir_channel(&b, clear_val, chan), nir_imm_int(&b, 0));
}
return b.shader;

67
src/amd/vulkan/radv_meta_clear.c
View file

@ -51,20 +51,14 @@ build_color_shaders(struct nir_shader **out_vs,
"gl_Position");
vs_out_pos->data.location = VARYING_SLOT_POS;
nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(in_color_load, 0);
nir_intrinsic_set_range(in_color_load, 16);
in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
in_color_load->num_components = 4;
nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 4, 32, "clear color");
nir_builder_instr_insert(&fs_b, &in_color_load->instr);
nir_ssa_def *in_color_load = nir_load_push_constant(&fs_b, 4, 32, nir_imm_int(&fs_b, 0), .range=16);
nir_variable *fs_out_color =
nir_variable_create(fs_b.shader, nir_var_shader_out, color_type,
"f_color");
fs_out_color->data.location = FRAG_RESULT_DATA0 + frag_output;
nir_store_var(&fs_b, fs_out_color, &in_color_load->dest.ssa, 0xf);
nir_store_var(&fs_b, fs_out_color, in_color_load, 0xf);
nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&vs_b);
nir_store_var(&vs_b, vs_out_pos, outvec, 0xf);
@ -517,31 +511,17 @@ build_depthstencil_shader(struct nir_shader **out_vs,
nir_ssa_def *z;
if (unrestricted) {
nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(in_color_load, 0);
nir_intrinsic_set_range(in_color_load, 4);
in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0));
in_color_load->num_components = 1;
nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
nir_builder_instr_insert(&fs_b, &in_color_load->instr);
nir_ssa_def *in_color_load = nir_load_push_constant(&fs_b, 1, 32, nir_imm_int(&fs_b, 0), .range=4);
nir_variable *fs_out_depth =
nir_variable_create(fs_b.shader, nir_var_shader_out,
glsl_int_type(), "f_depth");
fs_out_depth->data.location = FRAG_RESULT_DEPTH;
nir_store_var(&fs_b, fs_out_depth, &in_color_load->dest.ssa, 0x1);
nir_store_var(&fs_b, fs_out_depth, in_color_load, 0x1);
z = nir_imm_float(&vs_b, 0.0);
} else {
nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(in_color_load, 0);
nir_intrinsic_set_range(in_color_load, 4);
in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0));
in_color_load->num_components = 1;
nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value");
nir_builder_instr_insert(&vs_b, &in_color_load->instr);
z = &in_color_load->dest.ssa;
z = nir_load_push_constant(&vs_b, 1, 32, nir_imm_int(&vs_b, 0), .range=4);
}
nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, z);
@ -1175,41 +1155,16 @@ build_clear_htile_mask_shader()
nir_ssa_def *buf = radv_meta_load_descriptor(&b, 0, 0);
nir_intrinsic_instr *constants =
nir_intrinsic_instr_create(b.shader,
nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(constants, 0);
nir_intrinsic_set_range(constants, 8);
constants->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
constants->num_components = 2;
nir_ssa_dest_init(&constants->instr, &constants->dest, 2, 32, "constants");
nir_builder_instr_insert(&b, &constants->instr);
nir_ssa_def *constants = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range=8);
nir_intrinsic_instr *load =
nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(buf);
load->src[1] = nir_src_for_ssa(offset);
nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
load->num_components = 4;
nir_intrinsic_set_align(load, 16, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *load = nir_load_ssbo(&b, 4, 32, buf, offset, .align_mul=16);
/* data = (data & ~htile_mask) | (htile_value & htile_mask) */
nir_ssa_def *data =
nir_iand(&b, &load->dest.ssa,
nir_channel(&b, &constants->dest.ssa, 1));
data = nir_ior(&b, data, nir_channel(&b, &constants->dest.ssa, 0));
nir_ssa_def *data = nir_iand(&b, load, nir_channel(&b, constants, 1));
data = nir_ior(&b, data, nir_channel(&b, constants, 0));
nir_intrinsic_instr *store =
nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(data);
store->src[1] = nir_src_for_ssa(buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
nir_intrinsic_set_align(store, 16, 0);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, data, buf, offset, .write_mask=0xf,
.access=ACCESS_NON_READABLE, .align_mul=16);
return b.shader;
}

19
src/amd/vulkan/radv_meta_fast_clear.c
View file

@ -82,19 +82,14 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
nir_builder_instr_insert(&b, &tex->instr);
nir_scoped_barrier(&b, NIR_SCOPE_WORKGROUP, NIR_SCOPE_WORKGROUP,
NIR_MEMORY_ACQ_REL, nir_var_mem_ssbo);
nir_scoped_barrier(&b, .execution_scope=NIR_SCOPE_WORKGROUP,
.memory_scope=NIR_SCOPE_WORKGROUP,
.memory_semantics=NIR_MEMORY_ACQ_REL,
.memory_modes=nir_var_mem_ssbo);
nir_ssa_def *outval = &tex->dest.ssa;
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(global_id);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
global_id, nir_ssa_undef(&b, 1, 32), &tex->dest.ssa,
nir_imm_int(&b, 0));
return b.shader;
}

12
src/amd/vulkan/radv_meta_fmask_expand.c
View file

@ -88,16 +88,8 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples)
for (uint32_t i = 0; i < samples; i++) {
nir_ssa_def *outval = &tex_instr[i]->dest.ssa;
nir_intrinsic_instr *store =
nir_intrinsic_instr_create(b.shader,
nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(output_img_deref);
store->src[1] = nir_src_for_ssa(global_id);
store->src[2] = nir_src_for_ssa(nir_imm_int(&b, i));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_image_deref_store(&b, output_img_deref, global_id, nir_imm_int(&b, i),
outval, nir_imm_int(&b, 0));
}
return b.shader;

62
src/amd/vulkan/radv_meta_resolve_cs.c
View file

@ -100,23 +100,10 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 16);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = 2;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *dst_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range=16);
nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(dst_offset, 0);
nir_intrinsic_set_range(dst_offset, 16);
dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
dst_offset->num_components = 2;
nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
nir_builder_instr_insert(&b, &dst_offset->instr);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, src_offset), 0x3);
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
@ -126,15 +113,9 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
if (is_srgb)
outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_ssa_def *coord = nir_iadd(&b, global_id, dst_offset);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
return b.shader;
}
@ -199,23 +180,10 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 16);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = 2;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *dst_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range=16);
nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(dst_offset, 0);
nir_intrinsic_set_range(dst_offset, 16);
dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
dst_offset->num_components = 2;
nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
nir_builder_instr_insert(&b, &dst_offset->instr);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, src_offset), 0x3);
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
@ -283,15 +251,9 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
}
nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
store->num_components = 4;
store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
store->src[1] = nir_src_for_ssa(coord);
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(outval);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_builder_instr_insert(&b, &store->instr);
nir_ssa_def *coord = nir_iadd(&b, global_id, dst_offset);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa,
coord, nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
return b.shader;
}

20
src/amd/vulkan/radv_meta_resolve_fs.c
View file

@ -68,17 +68,11 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
color_out->data.location = FRAG_RESULT_DATA0;
nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 8);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = 2;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), 0, 8);
nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, src_offset), 0x3);
nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
@ -376,17 +370,11 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(src_offset, 0);
nir_intrinsic_set_range(src_offset, 8);
src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
src_offset->num_components = 2;
nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
nir_builder_instr_insert(&b, &src_offset->instr);
nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), 0, 8);
nir_ssa_def *pos_int = nir_f2i32(&b, pos_in);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, &src_offset->dest.ssa), 0x3);
nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, pos_int, src_offset), 0x3);
nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;

251
src/amd/vulkan/radv_query.c
View file

@ -66,19 +66,6 @@ static void radv_break_on_count(nir_builder *b, nir_variable *var, nir_ssa_def *
nir_store_var(b, var, counter, 0x1);
}
static struct nir_ssa_def *
radv_load_push_int(nir_builder *b, unsigned offset, const char *name)
{
nir_intrinsic_instr *flags = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(flags, 0);
nir_intrinsic_set_range(flags, 16);
flags->src[0] = nir_src_for_ssa(nir_imm_int(b, offset));
flags->num_components = 1;
nir_ssa_dest_init(&flags->instr, &flags->dest, 1, 32, name);
nir_builder_instr_insert(b, &flags->instr);
return &flags->dest.ssa;
}
static void
radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def *dst_buf,
nir_ssa_def *offset, nir_ssa_def *value32)
@ -87,25 +74,12 @@ radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def *dst_buf
nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_64_BIT));
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_vec2(b, value32, nir_imm_int(b, 0)));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0x3);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 2;
nir_builder_instr_insert(b, &store->instr);
nir_store_ssbo(b, nir_vec2(b, value32, nir_imm_int(b, 0)),
dst_buf, offset, .write_mask=0x3, .align_mul=8);
nir_push_else(b, NULL);
store = nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(value32);
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 1;
nir_builder_instr_insert(b, &store->instr);
nir_store_ssbo(b, value32, dst_buf, offset, .write_mask=0x1, .align_mul=4);
nir_pop_if(b, NULL);
@ -166,7 +140,7 @@ build_occlusion_query_shader(struct radv_device *device) {
unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
unsigned db_count = device->physical_device->rad_info.max_render_backends;
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);
@ -182,7 +156,7 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_ssa_def *input_stride = nir_imm_int(&b, db_count * 16);
nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range=16);
nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
@ -204,16 +178,10 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
load_offset = nir_iadd(&b, input_base, load_offset);
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(load_offset);
nir_ssa_dest_init(&load->instr, &load->dest, 2, 64, NULL);
load->num_components = 2;
nir_intrinsic_set_align(load, 16, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *load = nir_load_ssbo(&b, 2, 64, src_buf, load_offset, .align_mul=16);
nir_store_var(&b, start, nir_channel(&b, &load->dest.ssa, 0), 0x1);
nir_store_var(&b, end, nir_channel(&b, &load->dest.ssa, 1), 0x1);
nir_store_var(&b, start, nir_channel(&b, load, 0), 0x1);
nir_store_var(&b, end, nir_channel(&b, load, 1), 0x1);
nir_ssa_def *start_done = nir_ilt(&b, nir_load_var(&b, start), nir_imm_int64(&b, 0));
nir_ssa_def *end_done = nir_ilt(&b, nir_load_var(&b, end), nir_imm_int64(&b, 0));
@ -244,25 +212,13 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_push_if(&b, result_is_64bit);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base,
.write_mask=0x1, .align_mul=8);
nir_push_else(&b, NULL);
store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf,
output_base, .write_mask=0x1, .align_mul=8);
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@ -326,9 +282,9 @@ build_pipeline_statistics_query_shader(struct radv_device *device) {
nir_variable *output_offset = nir_local_variable_create(b.impl, glsl_int_type(), "output_offset");
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
nir_ssa_def *stats_mask = radv_load_push_int(&b, 8, "stats_mask");
nir_ssa_def *avail_offset = radv_load_push_int(&b, 12, "avail_offset");
nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range=16);
nir_ssa_def *stats_mask = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 8), .range=16);
nir_ssa_def *avail_offset = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 12), .range=16);
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);
@ -344,21 +300,14 @@ build_pipeline_statistics_query_shader(struct radv_device *device) {
nir_ssa_def *input_stride = nir_imm_int(&b, pipelinestat_block_size * 2);
nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range=16);
nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
avail_offset = nir_iadd(&b, avail_offset,
nir_imul(&b, global_id, nir_imm_int(&b, 4)));
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(avail_offset);
nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
load->num_components = 1;
nir_intrinsic_set_align(load, 4, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *available32 = &load->dest.ssa;
nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset, .align_mul=4);
nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT);
nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4));
@ -374,50 +323,26 @@ build_pipeline_statistics_query_shader(struct radv_device *device) {
for (int i = 0; i < ARRAY_SIZE(pipeline_statistics_indices); ++i) {
nir_push_if(&b, nir_test_flag(&b, stats_mask, 1u << i));
load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
nir_imm_int(&b, pipeline_statistics_indices[i] * 8)));
nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
load->num_components = 1;
nir_intrinsic_set_align(load, 8, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *start = &load->dest.ssa;
nir_ssa_def *start_offset = nir_iadd(&b, input_base,
nir_imm_int(&b, pipeline_statistics_indices[i] * 8));
nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset, .align_mul=8);
load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base,
nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size)));
nir_ssa_dest_init(&load->instr, &load->dest, 1, 64, NULL);
load->num_components = 1;
nir_intrinsic_set_align(load, 8, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *end = &load->dest.ssa;
nir_ssa_def *end_offset = nir_iadd(&b, input_base,
nir_imm_int(&b, pipeline_statistics_indices[i] * 8 + pipelinestat_block_size));
nir_ssa_def *end = nir_load_ssbo(&b, 1, 64, src_buf, end_offset, .align_mul=8);
nir_ssa_def *result = nir_isub(&b, end, start);
/* Store result */
nir_push_if(&b, result_is_64bit);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(result);
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, result, dst_buf, nir_load_var(&b, output_offset),
.write_mask=0x1, .align_mul=8);
nir_push_else(&b, NULL);
store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_u2u32(&b, result));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(nir_load_var(&b, output_offset));
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_u2u32(&b, result), dst_buf, nir_load_var(&b, output_offset),
.write_mask=0x1, .align_mul=4);
nir_pop_if(&b, NULL);
@ -446,25 +371,13 @@ build_pipeline_statistics_query_shader(struct radv_device *device) {
nir_imul(&b, elem_size, current_counter));
nir_push_if(&b, result_is_64bit);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_imm_int64(&b, 0));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_elem);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_imm_int64(&b, 0), dst_buf, output_elem,
.write_mask=0x1, .align_mul=8);
nir_push_else(&b, NULL);
store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_elem);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_imm_int(&b, 0), dst_buf, output_elem,
.write_mask=0x1, .align_mul=4);
nir_pop_if(&b, NULL);
@ -530,7 +443,7 @@ build_tfb_query_shader(struct radv_device *device)
nir_imm_int64(&b, 0)), 0x3);
nir_store_var(&b, available, nir_imm_false(&b), 0x1);
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range=16);
/* Load resources. */
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
@ -549,32 +462,21 @@ build_tfb_query_shader(struct radv_device *device)
/* Compute src/dst strides. */
nir_ssa_def *input_stride = nir_imm_int(&b, 32);
nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range=16);
nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_intrinsic_instr *load1 = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load1->src[0] = nir_src_for_ssa(src_buf);
load1->src[1] = nir_src_for_ssa(input_base);
nir_ssa_dest_init(&load1->instr, &load1->dest, 4, 32, NULL);
load1->num_components = 4;
nir_intrinsic_set_align(load1, 32, 0);
nir_builder_instr_insert(&b, &load1->instr);
nir_intrinsic_instr *load2 = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load2->src[0] = nir_src_for_ssa(src_buf);
load2->src[1] = nir_src_for_ssa(nir_iadd(&b, input_base, nir_imm_int(&b, 16)));
nir_ssa_dest_init(&load2->instr, &load2->dest, 4, 32, NULL);
load2->num_components = 4;
nir_intrinsic_set_align(load2, 16, 0);
nir_builder_instr_insert(&b, &load2->instr);
nir_ssa_def *load1 = nir_load_ssbo(&b, 4, 32, src_buf, input_base, .align_mul=32);
nir_ssa_def *load2 = nir_load_ssbo(&b, 4, 32, src_buf,
nir_iadd(&b, input_base, nir_imm_int(&b, 16)),
.align_mul=16);
/* Check if result is available. */
nir_ssa_def *avails[2];
avails[0] = nir_iand(&b, nir_channel(&b, &load1->dest.ssa, 1),
nir_channel(&b, &load1->dest.ssa, 3));
avails[1] = nir_iand(&b, nir_channel(&b, &load2->dest.ssa, 1),
nir_channel(&b, &load2->dest.ssa, 3));
avails[0] = nir_iand(&b, nir_channel(&b, load1, 1),
nir_channel(&b, load1, 3));
avails[1] = nir_iand(&b, nir_channel(&b, load2, 1),
nir_channel(&b, load2, 3));
nir_ssa_def *result_is_available =
nir_i2b(&b, nir_iand(&b, nir_iand(&b, avails[0], avails[1]),
nir_imm_int(&b, 0x80000000)));
@ -585,17 +487,17 @@ build_tfb_query_shader(struct radv_device *device)
/* Pack values. */
nir_ssa_def *packed64[4];
packed64[0] = nir_pack_64_2x32(&b, nir_vec2(&b,
nir_channel(&b, &load1->dest.ssa, 0),
nir_channel(&b, &load1->dest.ssa, 1)));
nir_channel(&b, load1, 0),
nir_channel(&b, load1, 1)));
packed64[1] = nir_pack_64_2x32(&b, nir_vec2(&b,
nir_channel(&b, &load1->dest.ssa, 2),
nir_channel(&b, &load1->dest.ssa, 3)));
nir_channel(&b, load1, 2),
nir_channel(&b, load1, 3)));
packed64[2] = nir_pack_64_2x32(&b, nir_vec2(&b,
nir_channel(&b, &load2->dest.ssa, 0),
nir_channel(&b, &load2->dest.ssa, 1)));
nir_channel(&b, load2, 0),
nir_channel(&b, load2, 1)));
packed64[3] = nir_pack_64_2x32(&b, nir_vec2(&b,
nir_channel(&b, &load2->dest.ssa, 2),
nir_channel(&b, &load2->dest.ssa, 3)));
nir_channel(&b, load2, 2),
nir_channel(&b, load2, 3)));
/* Compute result. */
nir_ssa_def *num_primitive_written =
@ -626,25 +528,13 @@ build_tfb_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x3);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 2;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base,
.write_mask=0x3, .align_mul=8);
nir_push_else(&b, NULL);
store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x3);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 2;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf,
output_base, .write_mask=0x3, .align_mul=4);
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@ -703,7 +593,7 @@ build_timestamp_query_shader(struct radv_device *device)
nir_store_var(&b, result, nir_imm_int64(&b, 0), 0x1);
nir_store_var(&b, available, nir_imm_false(&b), 0x1);
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
nir_ssa_def *flags = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 0), .range=16);
/* Load resources. */
nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
@ -722,23 +612,17 @@ build_timestamp_query_shader(struct radv_device *device)
/* Compute src/dst strides. */
nir_ssa_def *input_stride = nir_imm_int(&b, 8);
nir_ssa_def *input_base = nir_imul(&b, input_stride, global_id);
nir_ssa_def *output_stride = radv_load_push_int(&b, 4, "output_stride");
nir_ssa_def *output_stride = nir_load_push_constant(&b, 1, 32, nir_imm_int(&b, 4), .range=16);
nir_ssa_def *output_base = nir_imul(&b, output_stride, global_id);
/* Load data from the query pool. */
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(input_base);
nir_ssa_dest_init(&load->instr, &load->dest, 2, 32, NULL);
load->num_components = 2;
nir_intrinsic_set_align(load, 8, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_ssa_def *load = nir_load_ssbo(&b, 2, 32, src_buf, input_base, .align_mul=8);
/* Pack the timestamp. */
nir_ssa_def *timestamp;
timestamp = nir_pack_64_2x32(&b, nir_vec2(&b,
nir_channel(&b, &load->dest.ssa, 0),
nir_channel(&b, &load->dest.ssa, 1)));
nir_channel(&b, load, 0),
nir_channel(&b, load, 1)));
/* Check if result is available. */
nir_ssa_def *result_is_available =
@ -767,25 +651,12 @@ build_timestamp_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_load_var(&b, result));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 8, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_load_var(&b, result), dst_buf, output_base, .write_mask=0x1, .align_mul=8);
nir_push_else(&b, NULL);
store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_u2u32(&b, nir_load_var(&b, result)));
store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(output_base);
nir_intrinsic_set_write_mask(store, 0x1);
nir_intrinsic_set_align(store, 4, 0);
store->num_components = 1;
nir_builder_instr_insert(&b, &store->instr);
nir_store_ssbo(&b, nir_u2u32(&b, nir_load_var(&b, result)), dst_buf,
output_base, .write_mask=0x1, .align_mul=4);
nir_pop_if(&b, NULL);