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aco: move VADDR to the end of the operand list

Browse source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8523>
This commit is contained in:
Rhys Perry 2021-01-14 17:46:50 +00:00 • committed by Marge Bot
parent cd29210fce
commit faf3e9a27f
7 changed files with 23 additions and 25 deletions
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6
src/amd/compiler/aco_assembler.cpp
View file

@ -448,11 +448,11 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
}
encoding |= (0xF & mimg->dmask) << 8;
out.push_back(encoding);
encoding = (0xFF & instr->operands[2].physReg()); /* VADDR */
encoding = (0xFF & instr->operands[3].physReg()); /* VADDR */
if (!instr->definitions.empty()) {
encoding |= (0xFF & instr->definitions[0].physReg()) << 8; /* VDATA */
} else if (instr->operands.size() >= 4) {
encoding |= (0xFF & instr->operands[3].physReg()) << 8; /* VDATA */
} else if (!instr->operands[2].isUndefined()) {
encoding |= (0xFF & instr->operands[2].physReg()) << 8; /* VDATA */
}
encoding |= (0x1F & (instr->operands[0].physReg() >> 2)) << 16; /* T# (resource) */
if (!instr->operands[1].isUndefined())

4
src/amd/compiler/aco_insert_waitcnt.cpp
View file

@ -850,10 +850,10 @@ void gen(Instruction* instr, wait_ctx& ctx)
insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock);
} else if (ctx.chip_class == GFX6 &&
instr->format == Format::MIMG &&
instr->operands.size() >= 4) {
!instr->operands[2].isUndefined()) {
ctx.exp_cnt++;
update_counters(ctx, event_vmem_gpr_lock);
insert_wait_entry(ctx, instr->operands[3], event_vmem_gpr_lock);
insert_wait_entry(ctx, instr->operands[2], event_vmem_gpr_lock);
}
break;

7
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -5866,14 +5866,13 @@ static MIMG_instruction *emit_mimg(Builder& bld, aco_opcode op,
}
aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(
op, Format::MIMG, 3 + !vdata.isUndefined(), dst.isTemp())};
op, Format::MIMG, 4, dst.isTemp())};
if (dst.isTemp())
mimg->definitions[0] = dst;
mimg->operands[0] = Operand(rsrc);
mimg->operands[1] = samp;
mimg->operands[2] = Operand(coord);
if (!vdata.isUndefined())
mimg->operands[3] = vdata;
mimg->operands[2] = vdata;
mimg->operands[3] = Operand(coord);
MIMG_instruction *res = mimg.get();
bld.insert(std::move(mimg));

4
src/amd/compiler/aco_ir.h
View file

@ -1290,8 +1290,8 @@ static_assert(sizeof(MTBUF_instruction) == sizeof(Instruction) + 8, "Unexpected
* Vector Memory Image Instructions
* Operand(0) SRSRC - Scalar GPR that specifies the resource constant.
* Operand(1): SSAMP - Scalar GPR that specifies sampler constant.
* Operand(2): VADDR - Address source. Can carry an offset or an index.
* Operand(3): VDATA - Vector GPR for write data or zero if TFE/LWE=1.
* Operand(2): VDATA - Vector GPR for write data or zero if TFE/LWE=1.
* Operand(3): VADDR - Address source. Can carry an offset or an index.
* Definition(0): VDATA - Vector GPR for read result.
*
*/

4
src/amd/compiler/aco_register_allocation.cpp
View file

@ -2199,8 +2199,8 @@ void register_allocation(Program *program, std::vector<IDSet>& live_out_per_bloc
instr->definitions[0].setFixed(instr->operands[3].physReg());
} else if (instr->format == Format::MIMG &&
instr->definitions.size() == 1 &&
instr->operands.size() >= 4) {
instr->definitions[0].setFixed(instr->operands[3].physReg());
!instr->operands[2].isUndefined()) {
instr->definitions[0].setFixed(instr->operands[2].physReg());
}
ctx.defs_done.reset();

15
src/amd/compiler/aco_validate.cpp
View file

@ -211,7 +211,7 @@ bool validate_ir(Program* program)
bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
instr->format == Format::PSEUDO_REDUCTION ||
instr->opcode == aco_opcode::p_create_vector ||
(flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
(flat && i == 1) || (instr->format == Format::MIMG && (i == 1 || i == 2)) ||
((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
} else {
@ -436,20 +436,19 @@ bool validate_ir(Program* program)
break;
}
case Format::MIMG: {
check(instr->operands.size() >= 3, "MIMG instructions must have 3 or 4 operands", instr.get());
check(instr->operands.size() <= 4, "MIMG instructions must have 3 or 4 operands", instr.get());
check(instr->operands.size() == 4, "MIMG instructions must have 4 operands", instr.get());
check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
"MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
if (instr->operands[1].hasRegClass())
check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
if (instr->operands.size() >= 4) {
if (!instr->operands[2].isUndefined()) {
bool is_cmpswap = instr->opcode == aco_opcode::image_atomic_cmpswap ||
instr->opcode == aco_opcode::image_atomic_fcmpswap;
check(instr->definitions.empty() || (instr->definitions[0].regClass() == instr->operands[3].regClass() || is_cmpswap),
"MIMG operands[3] (VDATA) must be the same as definitions[0] for atomics and TFE/LWE loads", instr.get());
check(instr->definitions.empty() || (instr->definitions[0].regClass() == instr->operands[2].regClass() || is_cmpswap),
"MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and TFE/LWE loads", instr.get());
}
check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
"MIMG operands[2] (VADDR) must be VGPR", instr.get());
check(instr->operands[3].hasRegClass() && instr->operands[3].regClass().type() == RegType::vgpr,
"MIMG operands[3] (VADDR) must be VGPR", instr.get());
check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
"MIMG definitions[0] (VDATA) must be VGPR", instr.get());
break;

8
src/amd/compiler/tests/test_isel.cpp
View file

@ -149,13 +149,13 @@ BEGIN_TEST(isel.sparse.clause)
};
void main() {
//>> v5: (noCSE)%zero0 = p_create_vector 0, 0, 0, 0, 0
//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero0 dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: %_ = image_sample_lz_o %_, %_, %zero0, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: (noCSE)%zero1 = p_create_vector 0, 0, 0, 0, 0
//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero1 dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: %_ = image_sample_lz_o %_, %_, %zero1, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: (noCSE)%zero2 = p_create_vector 0, 0, 0, 0, 0
//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero2 dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: %_ = image_sample_lz_o %_, %_, %zero2, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: (noCSE)%zero3 = p_create_vector 0, 0, 0, 0, 0
//>> v5: %_ = image_sample_lz_o %_, %_, %_, %zero3 dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> v5: %_ = image_sample_lz_o %_, %_, %zero3, %_ dmask:xyzw 2d tfe storage: semantics: scope:invocation
//>> s_clause 0x3
//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe
//! image_sample_lz_o v#_, v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D tfe