diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 35c65bd48df..c855066a8b1 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -3301,18 +3301,13 @@ radv_emit_mesh_shader(const struct radv_device *device, struct radeon_cmdbuf *ct
    const uint32_t gs_out = radv_conv_gl_prim_to_gs_out(ms->info.ms.output_prim);
 
    radv_emit_hw_ngg(device, ctx_cs, cs, NULL, ms);
-   radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
-                          pdev->mesh_fast_launch_2 ? ms->info.ngg_info.max_out_verts : ms->info.workgroup_size);
+   radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, ms->info.regs.ms.vgt_gs_max_vert_out);
    radeon_set_uconfig_reg_idx(pdev, ctx_cs, R_030908_VGT_PRIMITIVE_TYPE, 1, V_008958_DI_PT_POINTLIST);
 
    if (pdev->mesh_fast_launch_2) {
       radeon_set_sh_reg_seq(cs, R_00B2B0_SPI_SHADER_GS_MESHLET_DIM, 2);
-      radeon_emit(cs, S_00B2B0_MESHLET_NUM_THREAD_X(ms->info.cs.block_size[0] - 1) |
-                         S_00B2B0_MESHLET_NUM_THREAD_Y(ms->info.cs.block_size[1] - 1) |
-                         S_00B2B0_MESHLET_NUM_THREAD_Z(ms->info.cs.block_size[2] - 1) |
-                         S_00B2B0_MESHLET_THREADGROUP_SIZE(ms->info.workgroup_size - 1));
-      radeon_emit(cs, S_00B2B4_MAX_EXP_VERTS(ms->info.ngg_info.max_out_verts) |
-                         S_00B2B4_MAX_EXP_PRIMS(ms->info.ngg_info.prim_amp_factor));
+      radeon_emit(cs, ms->info.regs.ms.spi_shader_gs_meshlet_dim);
+      radeon_emit(cs, ms->info.regs.ms.spi_shader_gs_meshlet_exp_alloc);
    }
 
    radv_emit_vgt_gs_out(device, ctx_cs, gs_out);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index af4c5aeddc5..cbb8b96e710 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1476,6 +1476,23 @@ radv_precompute_registers_hw_gs(struct radv_device *device, struct radv_shader_b
                                       S_028A44_GS_INST_PRIMS_IN_SUBGRP(info->gs_ring_info.gs_inst_prims_in_subgroup);
 }
 
+static void
+radv_precompute_registers_hw_ms(struct radv_device *device, struct radv_shader_binary *binary)
+{
+   const struct radv_physical_device *pdev = radv_device_physical(device);
+   struct radv_shader_info *info = &binary->info;
+
+   info->regs.ms.vgt_gs_max_vert_out = pdev->mesh_fast_launch_2 ? info->ngg_info.max_out_verts : info->workgroup_size;
+
+   info->regs.ms.spi_shader_gs_meshlet_dim = S_00B2B0_MESHLET_NUM_THREAD_X(info->cs.block_size[0] - 1) |
+                                             S_00B2B0_MESHLET_NUM_THREAD_Y(info->cs.block_size[1] - 1) |
+                                             S_00B2B0_MESHLET_NUM_THREAD_Z(info->cs.block_size[2] - 1) |
+                                             S_00B2B0_MESHLET_THREADGROUP_SIZE(info->workgroup_size - 1);
+
+   info->regs.ms.spi_shader_gs_meshlet_exp_alloc =
+      S_00B2B4_MAX_EXP_VERTS(info->ngg_info.max_out_verts) | S_00B2B4_MAX_EXP_PRIMS(info->ngg_info.prim_amp_factor);
+}
+
 static void
 radv_precompute_registers_hw_fs(struct radv_device *device, struct radv_shader_binary *binary)
 {
@@ -1517,6 +1534,9 @@ radv_precompute_registers(struct radv_device *device, struct radv_shader_binary
       if (!info->is_ngg)
          radv_precompute_registers_hw_gs(device, binary);
       break;
+   case MESA_SHADER_MESH:
+      radv_precompute_registers_hw_ms(device, binary);
+      break;
    case MESA_SHADER_FRAGMENT:
       radv_precompute_registers_hw_fs(device, binary);
       break;
diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h
index 72e8b93b2c3..107cd9b2127 100644
--- a/src/amd/vulkan/radv_shader_info.h
+++ b/src/amd/vulkan/radv_shader_info.h
@@ -259,6 +259,12 @@ struct radv_shader_info {
          uint32_t vgt_gs_onchip_cntl;
       } gs;
 
+      struct {
+         uint32_t spi_shader_gs_meshlet_dim;
+         uint32_t spi_shader_gs_meshlet_exp_alloc;
+         uint32_t vgt_gs_max_vert_out;
+      } ms;
+
       struct {
          uint32_t pa_sc_shader_control;
          uint32_t spi_ps_in_control;