mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-04 20:00:11 +01:00
zink: break out descriptor updating into separate function
this is a massive block of code that we need to reuse for compute shaders because we absolutely don't want to be copying it around Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8781>
This commit is contained in:
Mike Blumenkrantz
Marge Bot
parent
b2247a3724
commit
fa555772b9
1 changed files with 194 additions and 174 deletions
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@ -216,143 +216,9 @@ get_gfx_program(struct zink_context *ctx)
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return ctx->curr_program;
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}
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static bool
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line_width_needed(enum pipe_prim_type reduced_prim,
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VkPolygonMode polygon_mode)
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static void
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update_descriptors(struct zink_context *ctx, struct zink_screen *screen, bool is_compute)
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{
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switch (reduced_prim) {
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case PIPE_PRIM_POINTS:
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return false;
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case PIPE_PRIM_LINES:
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return true;
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case PIPE_PRIM_TRIANGLES:
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return polygon_mode == VK_POLYGON_MODE_LINE;
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default:
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unreachable("unexpected reduced prim");
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}
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}
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static inline bool
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restart_supported(enum pipe_prim_type mode)
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{
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return mode == PIPE_PRIM_LINE_STRIP || mode == PIPE_PRIM_TRIANGLE_STRIP || mode == PIPE_PRIM_TRIANGLE_FAN;
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}
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void
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zink_draw_vbo(struct pipe_context *pctx,
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const struct pipe_draw_info *dinfo,
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const struct pipe_draw_indirect_info *dindirect,
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const struct pipe_draw_start_count *draws,
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unsigned num_draws)
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{
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if (num_draws > 1) {
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struct pipe_draw_info tmp_info = *dinfo;
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for (unsigned i = 0; i < num_draws; i++) {
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zink_draw_vbo(pctx, &tmp_info, dindirect, &draws[i], 1);
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if (tmp_info.increment_draw_id)
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tmp_info.drawid++;
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}
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return;
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}
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if (!dindirect && (!draws[0].count || !dinfo->instance_count))
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return;
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struct zink_context *ctx = zink_context(pctx);
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struct zink_screen *screen = zink_screen(pctx->screen);
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struct zink_rasterizer_state *rast_state = ctx->rast_state;
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struct zink_depth_stencil_alpha_state *dsa_state = ctx->dsa_state;
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struct zink_so_target *so_target =
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dindirect && dindirect->count_from_stream_output ?
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zink_so_target(dindirect->count_from_stream_output) : NULL;
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VkBuffer counter_buffers[PIPE_MAX_SO_OUTPUTS];
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VkDeviceSize counter_buffer_offsets[PIPE_MAX_SO_OUTPUTS] = {};
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bool need_index_buffer_unref = false;
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if (dinfo->primitive_restart && !restart_supported(dinfo->mode)) {
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util_draw_vbo_without_prim_restart(pctx, dinfo, dindirect, &draws[0]);
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return;
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}
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if (dinfo->mode == PIPE_PRIM_QUADS ||
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dinfo->mode == PIPE_PRIM_QUAD_STRIP ||
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dinfo->mode == PIPE_PRIM_POLYGON ||
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(dinfo->mode == PIPE_PRIM_TRIANGLE_FAN && !screen->have_triangle_fans) ||
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dinfo->mode == PIPE_PRIM_LINE_LOOP) {
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if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&draws[0].count))
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return;
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util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
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util_primconvert_draw_vbo(ctx->primconvert, dinfo, &draws[0]);
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return;
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}
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if (ctx->gfx_pipeline_state.vertices_per_patch != dinfo->vertices_per_patch)
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ctx->gfx_pipeline_state.dirty = true;
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ctx->gfx_pipeline_state.vertices_per_patch = dinfo->vertices_per_patch;
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struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
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if (!gfx_program)
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return;
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if (ctx->gfx_pipeline_state.primitive_restart != !!dinfo->primitive_restart)
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ctx->gfx_pipeline_state.dirty = true;
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ctx->gfx_pipeline_state.primitive_restart = !!dinfo->primitive_restart;
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for (unsigned i = 0; i < ctx->element_state->hw_state.num_bindings; i++) {
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unsigned binding = ctx->element_state->binding_map[i];
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const struct pipe_vertex_buffer *vb = ctx->buffers + binding;
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if (ctx->gfx_pipeline_state.bindings[i].stride != vb->stride) {
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ctx->gfx_pipeline_state.bindings[i].stride = vb->stride;
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ctx->gfx_pipeline_state.dirty = true;
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}
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}
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VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
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&ctx->gfx_pipeline_state,
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dinfo->mode);
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enum pipe_prim_type reduced_prim = u_reduced_prim(dinfo->mode);
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bool depth_bias = false;
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switch (reduced_prim) {
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case PIPE_PRIM_POINTS:
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depth_bias = rast_state->offset_point;
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break;
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case PIPE_PRIM_LINES:
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depth_bias = rast_state->offset_line;
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break;
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case PIPE_PRIM_TRIANGLES:
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depth_bias = rast_state->offset_tri;
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break;
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default:
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unreachable("unexpected reduced prim");
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}
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unsigned index_offset = 0;
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struct pipe_resource *index_buffer = NULL;
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if (dinfo->index_size > 0) {
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uint32_t restart_index = util_prim_restart_index_from_size(dinfo->index_size);
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if ((dinfo->primitive_restart && (dinfo->restart_index != restart_index)) ||
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(!screen->info.have_EXT_index_type_uint8 && dinfo->index_size == 1)) {
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util_translate_prim_restart_ib(pctx, dinfo, dindirect, &draws[0], &index_buffer);
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need_index_buffer_unref = true;
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} else {
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if (dinfo->has_user_indices) {
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if (!util_upload_index_buffer(pctx, dinfo, &draws[0], &index_buffer, &index_offset, 4)) {
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debug_printf("util_upload_index_buffer() failed\n");
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return;
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}
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} else
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index_buffer = dinfo->index.resource;
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}
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}
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VkWriteDescriptorSet wds[PIPE_SHADER_TYPES * (PIPE_MAX_CONSTANT_BUFFERS + PIPE_MAX_SAMPLERS + PIPE_MAX_SHADER_BUFFERS + PIPE_MAX_SHADER_IMAGES)];
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struct zink_resource *read_desc_resources[PIPE_SHADER_TYPES * (PIPE_MAX_CONSTANT_BUFFERS + PIPE_MAX_SAMPLERS + PIPE_MAX_SHADER_BUFFERS + PIPE_MAX_SHADER_IMAGES)] = {};
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struct zink_resource *write_desc_resources[PIPE_SHADER_TYPES * (PIPE_MAX_CONSTANT_BUFFERS + PIPE_MAX_SAMPLERS + PIPE_MAX_SHADER_BUFFERS + PIPE_MAX_SHADER_IMAGES)] = {};
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@ -360,7 +226,11 @@ zink_draw_vbo(struct pipe_context *pctx,
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VkDescriptorBufferInfo buffer_infos[PIPE_SHADER_TYPES * (PIPE_MAX_CONSTANT_BUFFERS + PIPE_MAX_SHADER_BUFFERS + PIPE_MAX_SHADER_IMAGES)];
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VkDescriptorImageInfo image_infos[PIPE_SHADER_TYPES * (PIPE_MAX_SAMPLERS + PIPE_MAX_SHADER_IMAGES)];
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VkBufferView buffer_view[] = {VK_NULL_HANDLE};
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int num_wds = 0, num_buffer_info = 0, num_image_info = 0, num_surface_refs = 0;
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unsigned num_wds = 0, num_buffer_info = 0, num_image_info = 0, num_surface_refs = 0;
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struct zink_shader **stages;
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unsigned num_stages = ZINK_SHADER_COUNT;
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stages = &ctx->gfx_stages[0];
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struct {
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struct zink_resource *res;
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@ -368,8 +238,8 @@ zink_draw_vbo(struct pipe_context *pctx,
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} transitions[PIPE_SHADER_TYPES * (PIPE_MAX_SAMPLERS + PIPE_MAX_SHADER_IMAGES)];
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int num_transitions = 0;
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for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
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struct zink_shader *shader = ctx->gfx_stages[i];
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for (int i = 0; i < num_stages; i++) {
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struct zink_shader *shader = stages[i];
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if (!shader)
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continue;
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enum pipe_shader_type stage = pipe_shader_type_from_mesa(shader->nir->info.stage);
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@ -534,31 +404,29 @@ zink_draw_vbo(struct pipe_context *pctx,
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transitions[i].layout);
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}
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if (ctx->xfb_barrier)
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zink_emit_xfb_counter_barrier(ctx);
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if (ctx->dirty_so_targets && ctx->num_so_targets)
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zink_emit_stream_output_targets(pctx);
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if (so_target && zink_resource(so_target->base.buffer)->needs_xfb_barrier)
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zink_emit_xfb_vertex_input_barrier(ctx, zink_resource(so_target->base.buffer));
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batch = zink_batch_rp(ctx);
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if (batch->descs_left < gfx_program->num_descriptors) {
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ctx->base.flush(&ctx->base, NULL, 0);
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unsigned num_descriptors;
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VkDescriptorSetLayout dsl;
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if (!is_compute) {
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batch = zink_batch_rp(ctx);
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assert(batch->descs_left >= gfx_program->num_descriptors);
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num_descriptors = ctx->curr_program->num_descriptors;
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dsl = ctx->curr_program->dsl;
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}
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if (batch->descs_left < num_descriptors) {
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if (!is_compute) {
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ctx->base.flush(&ctx->base, NULL, 0);
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batch = zink_batch_rp(ctx);
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}
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assert(batch->descs_left >= num_descriptors);
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}
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zink_batch_reference_program(batch, &ctx->curr_program->reference);
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VkDescriptorSet desc_set = allocate_descriptor_set(screen, batch,
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gfx_program->dsl, gfx_program->num_descriptors);
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dsl, num_descriptors);
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assert(desc_set != VK_NULL_HANDLE);
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for (int i = 0; i < ARRAY_SIZE(ctx->gfx_stages); i++) {
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struct zink_shader *shader = ctx->gfx_stages[i];
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for (int i = 0; i < num_stages; i++) {
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struct zink_shader *shader = stages[i];
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if (!shader)
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continue;
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enum pipe_shader_type stage = pipe_shader_type_from_mesa(shader->nir->info.stage);
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@ -573,6 +441,174 @@ zink_draw_vbo(struct pipe_context *pctx,
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}
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}
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if (num_wds > 0) {
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for (int i = 0; i < num_wds; ++i) {
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wds[i].dstSet = desc_set;
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if (read_desc_resources[i])
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zink_batch_reference_resource_rw(batch, read_desc_resources[i], false);
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else if (write_desc_resources[i])
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zink_batch_reference_resource_rw(batch, write_desc_resources[i], true);
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}
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vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
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for (int i = 0; i < num_surface_refs; i++) {
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if (surface_refs[i])
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zink_batch_reference_surface(batch, surface_refs[i]);
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}
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}
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vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
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ctx->curr_program->layout, 0, 1, &desc_set, 0, NULL);
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}
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static bool
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line_width_needed(enum pipe_prim_type reduced_prim,
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VkPolygonMode polygon_mode)
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{
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switch (reduced_prim) {
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case PIPE_PRIM_POINTS:
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return false;
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case PIPE_PRIM_LINES:
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return true;
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case PIPE_PRIM_TRIANGLES:
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return polygon_mode == VK_POLYGON_MODE_LINE;
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default:
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unreachable("unexpected reduced prim");
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}
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}
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static inline bool
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restart_supported(enum pipe_prim_type mode)
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{
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return mode == PIPE_PRIM_LINE_STRIP || mode == PIPE_PRIM_TRIANGLE_STRIP || mode == PIPE_PRIM_TRIANGLE_FAN;
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}
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void
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zink_draw_vbo(struct pipe_context *pctx,
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const struct pipe_draw_info *dinfo,
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const struct pipe_draw_indirect_info *dindirect,
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const struct pipe_draw_start_count *draws,
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unsigned num_draws)
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{
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if (num_draws > 1) {
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struct pipe_draw_info tmp_info = *dinfo;
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for (unsigned i = 0; i < num_draws; i++) {
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zink_draw_vbo(pctx, &tmp_info, dindirect, &draws[i], 1);
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if (tmp_info.increment_draw_id)
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tmp_info.drawid++;
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}
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return;
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}
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if (!dindirect && (!draws[0].count || !dinfo->instance_count))
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return;
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struct zink_context *ctx = zink_context(pctx);
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struct zink_screen *screen = zink_screen(pctx->screen);
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struct zink_rasterizer_state *rast_state = ctx->rast_state;
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struct zink_depth_stencil_alpha_state *dsa_state = ctx->dsa_state;
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struct zink_so_target *so_target =
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dindirect && dindirect->count_from_stream_output ?
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zink_so_target(dindirect->count_from_stream_output) : NULL;
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VkBuffer counter_buffers[PIPE_MAX_SO_OUTPUTS];
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VkDeviceSize counter_buffer_offsets[PIPE_MAX_SO_OUTPUTS] = {};
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bool need_index_buffer_unref = false;
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if (dinfo->primitive_restart && !restart_supported(dinfo->mode)) {
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util_draw_vbo_without_prim_restart(pctx, dinfo, dindirect, &draws[0]);
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return;
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}
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if (dinfo->mode == PIPE_PRIM_QUADS ||
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dinfo->mode == PIPE_PRIM_QUAD_STRIP ||
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dinfo->mode == PIPE_PRIM_POLYGON ||
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(dinfo->mode == PIPE_PRIM_TRIANGLE_FAN && !screen->have_triangle_fans) ||
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dinfo->mode == PIPE_PRIM_LINE_LOOP) {
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if (!u_trim_pipe_prim(dinfo->mode, (unsigned *)&draws[0].count))
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return;
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util_primconvert_save_rasterizer_state(ctx->primconvert, &rast_state->base);
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util_primconvert_draw_vbo(ctx->primconvert, dinfo, &draws[0]);
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return;
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}
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if (ctx->gfx_pipeline_state.vertices_per_patch != dinfo->vertices_per_patch)
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ctx->gfx_pipeline_state.dirty = true;
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ctx->gfx_pipeline_state.vertices_per_patch = dinfo->vertices_per_patch;
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struct zink_gfx_program *gfx_program = get_gfx_program(ctx);
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if (!gfx_program)
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return;
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if (ctx->gfx_pipeline_state.primitive_restart != !!dinfo->primitive_restart)
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ctx->gfx_pipeline_state.dirty = true;
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ctx->gfx_pipeline_state.primitive_restart = !!dinfo->primitive_restart;
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for (unsigned i = 0; i < ctx->element_state->hw_state.num_bindings; i++) {
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unsigned binding = ctx->element_state->binding_map[i];
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const struct pipe_vertex_buffer *vb = ctx->buffers + binding;
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if (ctx->gfx_pipeline_state.bindings[i].stride != vb->stride) {
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ctx->gfx_pipeline_state.bindings[i].stride = vb->stride;
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ctx->gfx_pipeline_state.dirty = true;
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}
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}
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VkPipeline pipeline = zink_get_gfx_pipeline(screen, gfx_program,
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&ctx->gfx_pipeline_state,
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dinfo->mode);
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enum pipe_prim_type reduced_prim = u_reduced_prim(dinfo->mode);
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bool depth_bias = false;
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switch (reduced_prim) {
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case PIPE_PRIM_POINTS:
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depth_bias = rast_state->offset_point;
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break;
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case PIPE_PRIM_LINES:
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depth_bias = rast_state->offset_line;
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break;
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case PIPE_PRIM_TRIANGLES:
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depth_bias = rast_state->offset_tri;
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break;
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default:
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unreachable("unexpected reduced prim");
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}
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unsigned index_offset = 0;
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struct pipe_resource *index_buffer = NULL;
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if (dinfo->index_size > 0) {
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uint32_t restart_index = util_prim_restart_index_from_size(dinfo->index_size);
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if ((dinfo->primitive_restart && (dinfo->restart_index != restart_index)) ||
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(!screen->info.have_EXT_index_type_uint8 && dinfo->index_size == 1)) {
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util_translate_prim_restart_ib(pctx, dinfo, dindirect, &draws[0], &index_buffer);
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need_index_buffer_unref = true;
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} else {
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if (dinfo->has_user_indices) {
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if (!util_upload_index_buffer(pctx, dinfo, &draws[0], &index_buffer, &index_offset, 4)) {
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debug_printf("util_upload_index_buffer() failed\n");
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return;
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}
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} else
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index_buffer = dinfo->index.resource;
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}
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}
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if (ctx->xfb_barrier)
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zink_emit_xfb_counter_barrier(ctx);
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if (ctx->dirty_so_targets && ctx->num_so_targets)
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zink_emit_stream_output_targets(pctx);
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if (so_target && zink_resource(so_target->base.buffer)->needs_xfb_barrier)
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zink_emit_xfb_vertex_input_barrier(ctx, zink_resource(so_target->base.buffer));
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update_descriptors(ctx, screen, false);
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struct zink_batch *batch = zink_batch_rp(ctx);
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vkCmdSetViewport(batch->cmdbuf, 0, ctx->gfx_pipeline_state.num_viewports, ctx->viewports);
|
||||
if (ctx->rast_state->base.scissor)
|
||||
vkCmdSetScissor(batch->cmdbuf, 0, ctx->gfx_pipeline_state.num_viewports, ctx->scissors);
|
||||
|
|
@ -613,24 +649,8 @@ zink_draw_vbo(struct pipe_context *pctx,
|
|||
if (ctx->gfx_pipeline_state.blend_state->need_blend_constants)
|
||||
vkCmdSetBlendConstants(batch->cmdbuf, ctx->blend_constants);
|
||||
|
||||
if (num_wds > 0) {
|
||||
for (int i = 0; i < num_wds; ++i) {
|
||||
wds[i].dstSet = desc_set;
|
||||
if (read_desc_resources[i])
|
||||
zink_batch_reference_resource_rw(batch, read_desc_resources[i], false);
|
||||
else if (write_desc_resources[i])
|
||||
zink_batch_reference_resource_rw(batch, write_desc_resources[i], true);
|
||||
}
|
||||
vkUpdateDescriptorSets(screen->dev, num_wds, wds, 0, NULL);
|
||||
for (int i = 0; i < num_surface_refs; i++) {
|
||||
if (surface_refs[i])
|
||||
zink_batch_reference_surface(batch, surface_refs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
|
||||
vkCmdBindDescriptorSets(batch->cmdbuf, VK_PIPELINE_BIND_POINT_GRAPHICS,
|
||||
gfx_program->layout, 0, 1, &desc_set, 0, NULL);
|
||||
|
||||
zink_bind_vertex_buffers(batch, ctx);
|
||||
|
||||
if (gfx_program->shaders[PIPE_SHADER_TESS_CTRL] && gfx_program->shaders[PIPE_SHADER_TESS_CTRL]->is_generated)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue