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anv: add texture cache inval after binding pool update

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Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31928>
This commit is contained in:
Lionel Landwerlin 2024-10-30 09:48:37 +00:00 • committed by Marge Bot
parent b3f487bd0d
commit f9e76e8ca6
1 changed files with 13 additions and 1 deletions
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14
src/intel/vulkan/genX_cmd_buffer.c
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@ -381,6 +381,17 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer)
struct anv_device *device = cmd_buffer->device;
const uint32_t mocs = isl_mocs(&device->isl_dev, 0, false);
/* We're changing base location of binding tables which affects the state
* cache. We're adding texture cache invalidation following a
* recommendation from the ICL PRMs, Volume 9: Render Engine, Coherency
* Mechanisms:
*
* "It is strongly recommended that a Texture cache invalidation be done
* whenever a State cache invalidation is done."
*
* Prior to do the invalidation, we need a CS_STALL to ensure that all work
* using surface states has completed.
*/
genx_batch_emit_pipe_control(&cmd_buffer->batch,
cmd_buffer->device->info,
cmd_buffer->state.current_pipeline,
@ -392,11 +403,12 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer)
btpa.BindingTablePoolBufferSize = device->physical->va.binding_table_pool.size / 4096;
btpa.MOCS = mocs;
}
genx_batch_emit_pipe_control(&cmd_buffer->batch,
cmd_buffer->device->info,
cmd_buffer->state.current_pipeline,
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT);
#else /* GFX_VERx10 < 125 */
genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
#endif