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util: move u_stub to src/util, add u_stub_gfx_compute.h

Browse source 
Move u_stub.h from amd/common, to util, so that it can be used in more
places.

Also, rename u_stub's PROC to MESAPROC, as it conflicts with the PROC
keyword and create a new TAILZ which returns 0.

Add u_stub_gfx_compute.h so that the following:

...can be a single-line:

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40493>
This commit is contained in:
Thong Thai 2026-03-25 21:50:01 +00:00 • committed by Marge Bot
parent c36e3ce934
commit f9df50eb31
6 changed files with 137 additions and 128 deletions
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120
src/amd/common/ac_linux_drm.h
View file

@ -327,7 +327,7 @@ extern "C" {
#ifdef _WIN32
#define __U_STUB__
#endif
#include "u_stub.h"
#include "util/u_stub.h"
struct ac_drm_device;
typedef struct ac_drm_device ac_drm_device;
@ -351,109 +351,109 @@ struct ac_drm_bo_import_result {
};
PROC int ac_drm_device_initialize(int fd, bool is_virtio,
MESAPROC int ac_drm_device_initialize(int fd, bool is_virtio,
uint32_t *major_version, uint32_t *minor_version,
ac_drm_device **device_handle) TAIL;
PROC struct util_sync_provider *ac_drm_device_get_sync_provider(ac_drm_device *dev) TAILPTR;
PROC uintptr_t ac_drm_device_get_cookie(ac_drm_device *dev) TAIL;
PROC void ac_drm_device_deinitialize(ac_drm_device *dev) TAILV;
PROC int ac_drm_device_get_fd(ac_drm_device *dev) TAIL;
PROC int ac_drm_bo_set_metadata(ac_drm_device *dev, uint32_t bo_handle,
MESAPROC struct util_sync_provider *ac_drm_device_get_sync_provider(ac_drm_device *dev) TAILPTR;
MESAPROC uintptr_t ac_drm_device_get_cookie(ac_drm_device *dev) TAIL;
MESAPROC void ac_drm_device_deinitialize(ac_drm_device *dev) TAILV;
MESAPROC int ac_drm_device_get_fd(ac_drm_device *dev) TAIL;
MESAPROC int ac_drm_bo_set_metadata(ac_drm_device *dev, uint32_t bo_handle,
struct amdgpu_bo_metadata *info) TAIL;
PROC int ac_drm_bo_query_info(ac_drm_device *dev, uint32_t bo_handle, struct amdgpu_bo_info *info) TAIL;
PROC int ac_drm_bo_wait_for_idle(ac_drm_device *dev, ac_drm_bo bo, uint64_t timeout_ns,
MESAPROC int ac_drm_bo_query_info(ac_drm_device *dev, uint32_t bo_handle, struct amdgpu_bo_info *info) TAIL;
MESAPROC int ac_drm_bo_wait_for_idle(ac_drm_device *dev, ac_drm_bo bo, uint64_t timeout_ns,
bool *busy) TAIL;
PROC int ac_drm_bo_va_op(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
MESAPROC int ac_drm_bo_va_op(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops) TAIL;
PROC int ac_drm_bo_va_op_raw(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
MESAPROC int ac_drm_bo_va_op_raw(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops) TAIL;
PROC int ac_drm_bo_va_op_raw2(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
MESAPROC int ac_drm_bo_va_op_raw2(ac_drm_device *dev, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops,
uint32_t vm_timeline_syncobj_out, uint64_t vm_timeline_point,
uint64_t input_fence_syncobj_handles,
uint32_t num_syncobj_handles) TAIL;
PROC int ac_drm_cs_ctx_create2(ac_drm_device *dev, uint32_t priority, uint32_t *ctx_id) TAIL;
PROC int ac_drm_cs_ctx_free(ac_drm_device *dev, uint32_t ctx_id) TAIL;
PROC int ac_drm_cs_ctx_stable_pstate(ac_drm_device *dev, uint32_t ctx_id, uint32_t op,
MESAPROC int ac_drm_cs_ctx_create2(ac_drm_device *dev, uint32_t priority, uint32_t *ctx_id) TAIL;
MESAPROC int ac_drm_cs_ctx_free(ac_drm_device *dev, uint32_t ctx_id) TAIL;
MESAPROC int ac_drm_cs_ctx_stable_pstate(ac_drm_device *dev, uint32_t ctx_id, uint32_t op,
uint32_t flags, uint32_t *out_flags) TAIL;
PROC int ac_drm_cs_query_reset_state2(ac_drm_device *dev, uint32_t ctx_id, uint64_t *flags) TAIL;
PROC int ac_drm_cs_query_fence_status(ac_drm_device *dev, uint32_t ctx_id, uint32_t ip_type,
MESAPROC int ac_drm_cs_query_reset_state2(ac_drm_device *dev, uint32_t ctx_id, uint64_t *flags) TAIL;
MESAPROC int ac_drm_cs_query_fence_status(ac_drm_device *dev, uint32_t ctx_id, uint32_t ip_type,
uint32_t ip_instance, uint32_t ring, uint64_t fence_seq_no,
uint64_t timeout_ns, uint64_t flags, uint32_t *expired) TAIL;
PROC int ac_drm_cs_create_syncobj2(ac_drm_device *dev, uint32_t flags, uint32_t *handle) TAIL;
PROC int ac_drm_cs_destroy_syncobj(ac_drm_device *dev, uint32_t handle) TAIL;
PROC int ac_drm_cs_syncobj_wait(ac_drm_device *dev, uint32_t *handles, unsigned num_handles,
MESAPROC int ac_drm_cs_create_syncobj2(ac_drm_device *dev, uint32_t flags, uint32_t *handle) TAIL;
MESAPROC int ac_drm_cs_destroy_syncobj(ac_drm_device *dev, uint32_t handle) TAIL;
MESAPROC int ac_drm_cs_syncobj_wait(ac_drm_device *dev, uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled) TAIL;
PROC int ac_drm_cs_syncobj_query2(ac_drm_device *dev, uint32_t *handles, uint64_t *points,
MESAPROC int ac_drm_cs_syncobj_query2(ac_drm_device *dev, uint32_t *handles, uint64_t *points,
unsigned num_handles, uint32_t flags) TAIL;
PROC int ac_drm_cs_import_syncobj(ac_drm_device *dev, int shared_fd, uint32_t *handle) TAIL;
PROC int ac_drm_cs_syncobj_export_sync_file(ac_drm_device *dev, uint32_t syncobj,
MESAPROC int ac_drm_cs_import_syncobj(ac_drm_device *dev, int shared_fd, uint32_t *handle) TAIL;
MESAPROC int ac_drm_cs_syncobj_export_sync_file(ac_drm_device *dev, uint32_t syncobj,
int *sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_import_sync_file(ac_drm_device *dev, uint32_t syncobj, int sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_export_sync_file2(ac_drm_device *dev, uint32_t syncobj, uint64_t point,
MESAPROC int ac_drm_cs_syncobj_import_sync_file(ac_drm_device *dev, uint32_t syncobj, int sync_file_fd) TAIL;
MESAPROC int ac_drm_cs_syncobj_export_sync_file2(ac_drm_device *dev, uint32_t syncobj, uint64_t point,
uint32_t flags, int *sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_transfer(ac_drm_device *dev, uint32_t dst_handle, uint64_t dst_point,
MESAPROC int ac_drm_cs_syncobj_transfer(ac_drm_device *dev, uint32_t dst_handle, uint64_t dst_point,
uint32_t src_handle, uint64_t src_point, uint32_t flags) TAIL;
PROC int ac_drm_cs_submit_raw2(ac_drm_device *dev, uint32_t ctx_id, uint32_t bo_list_handle,
MESAPROC int ac_drm_cs_submit_raw2(ac_drm_device *dev, uint32_t ctx_id, uint32_t bo_list_handle,
int num_chunks, struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no) TAIL;
PROC void ac_drm_cs_chunk_fence_info_to_data(uint32_t bo_handle, uint64_t offset,
MESAPROC void ac_drm_cs_chunk_fence_info_to_data(uint32_t bo_handle, uint64_t offset,
struct drm_amdgpu_cs_chunk_data *data) TAILV;
PROC int ac_drm_cs_syncobj_timeline_wait(ac_drm_device *dev, uint32_t *handles, uint64_t *points,
MESAPROC int ac_drm_cs_syncobj_timeline_wait(ac_drm_device *dev, uint32_t *handles, uint64_t *points,
unsigned num_handles, int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled) TAIL;
PROC int ac_drm_query_info(ac_drm_device *dev, unsigned info_id, unsigned size, void *value) TAIL;
PROC int ac_drm_read_mm_registers(ac_drm_device *dev, unsigned dword_offset, unsigned count,
MESAPROC int ac_drm_query_info(ac_drm_device *dev, unsigned info_id, unsigned size, void *value) TAIL;
MESAPROC int ac_drm_read_mm_registers(ac_drm_device *dev, unsigned dword_offset, unsigned count,
uint32_t instance, uint32_t flags, uint32_t *values) TAIL;
PROC int ac_drm_query_hw_ip_count(ac_drm_device *dev, unsigned type, uint32_t *count) TAIL;
PROC int ac_drm_query_hw_ip_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
MESAPROC int ac_drm_query_hw_ip_count(ac_drm_device *dev, unsigned type, uint32_t *count) TAIL;
MESAPROC int ac_drm_query_hw_ip_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info) TAIL;
PROC int ac_drm_query_firmware_version(ac_drm_device *dev, unsigned fw_type, unsigned ip_instance,
MESAPROC int ac_drm_query_firmware_version(ac_drm_device *dev, unsigned fw_type, unsigned ip_instance,
unsigned index, uint32_t *version, uint32_t *feature) TAIL;
PROC int ac_drm_query_uq_fw_area_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
MESAPROC int ac_drm_query_uq_fw_area_info(ac_drm_device *dev, unsigned type, unsigned ip_instance,
struct drm_amdgpu_info_uq_metadata *info) TAIL;
PROC int ac_drm_query_gpu_info(ac_drm_device *dev, struct amdgpu_gpu_info *info) TAIL;
PROC int ac_drm_query_heap_info(ac_drm_device *dev, uint32_t heap, uint32_t flags,
MESAPROC int ac_drm_query_gpu_info(ac_drm_device *dev, struct amdgpu_gpu_info *info) TAIL;
MESAPROC int ac_drm_query_heap_info(ac_drm_device *dev, uint32_t heap, uint32_t flags,
struct amdgpu_heap_info *info) TAIL;
PROC int ac_drm_query_sensor_info(ac_drm_device *dev, unsigned sensor_type, unsigned size,
MESAPROC int ac_drm_query_sensor_info(ac_drm_device *dev, unsigned sensor_type, unsigned size,
void *value) TAIL;
PROC int ac_drm_query_video_caps_info(ac_drm_device *dev, unsigned cap_type, unsigned size,
MESAPROC int ac_drm_query_video_caps_info(ac_drm_device *dev, unsigned cap_type, unsigned size,
void *value) TAIL;
PROC int ac_drm_query_gpuvm_fault_info(ac_drm_device *dev, unsigned size, void *value) TAIL;
PROC int ac_drm_vm_reserve_vmid(ac_drm_device *dev, uint32_t flags) TAIL;
PROC int ac_drm_vm_unreserve_vmid(ac_drm_device *dev, uint32_t flags) TAIL;
PROC const char *ac_drm_get_marketing_name(ac_drm_device *device) TAILPTR;
PROC int ac_drm_query_sw_info(ac_drm_device *dev,
MESAPROC int ac_drm_query_gpuvm_fault_info(ac_drm_device *dev, unsigned size, void *value) TAIL;
MESAPROC int ac_drm_vm_reserve_vmid(ac_drm_device *dev, uint32_t flags) TAIL;
MESAPROC int ac_drm_vm_unreserve_vmid(ac_drm_device *dev, uint32_t flags) TAIL;
MESAPROC const char *ac_drm_get_marketing_name(ac_drm_device *device) TAILPTR;
MESAPROC int ac_drm_query_sw_info(ac_drm_device *dev,
enum amdgpu_sw_info info, void *value) TAIL;
PROC int ac_drm_bo_alloc(ac_drm_device *dev, struct amdgpu_bo_alloc_request *alloc_buffer,
MESAPROC int ac_drm_bo_alloc(ac_drm_device *dev, struct amdgpu_bo_alloc_request *alloc_buffer,
ac_drm_bo *bo) TAIL;
PROC int ac_drm_bo_export(ac_drm_device *dev, ac_drm_bo bo,
MESAPROC int ac_drm_bo_export(ac_drm_device *dev, ac_drm_bo bo,
enum amdgpu_bo_handle_type type, uint32_t *shared_handle) TAIL;
PROC int ac_drm_bo_import(ac_drm_device *dev, enum amdgpu_bo_handle_type type,
MESAPROC int ac_drm_bo_import(ac_drm_device *dev, enum amdgpu_bo_handle_type type,
uint32_t shared_handle, struct ac_drm_bo_import_result *output) TAIL;
PROC int ac_drm_create_bo_from_user_mem(ac_drm_device *dev, void *cpu,
MESAPROC int ac_drm_create_bo_from_user_mem(ac_drm_device *dev, void *cpu,
uint64_t size, ac_drm_bo *bo) TAIL;
PROC int ac_drm_bo_free(ac_drm_device *dev, ac_drm_bo bo) TAIL;
PROC int ac_drm_bo_cpu_map(ac_drm_device *dev, ac_drm_bo bo, void **cpu) TAIL;
PROC int ac_drm_bo_cpu_unmap(ac_drm_device *dev, ac_drm_bo bo) TAIL;
PROC int ac_drm_va_range_alloc(ac_drm_device *dev, enum amdgpu_gpu_va_range va_range_type,
MESAPROC int ac_drm_bo_free(ac_drm_device *dev, ac_drm_bo bo) TAIL;
MESAPROC int ac_drm_bo_cpu_map(ac_drm_device *dev, ac_drm_bo bo, void **cpu) TAIL;
MESAPROC int ac_drm_bo_cpu_unmap(ac_drm_device *dev, ac_drm_bo bo) TAIL;
MESAPROC int ac_drm_va_range_alloc(ac_drm_device *dev, enum amdgpu_gpu_va_range va_range_type,
uint64_t size, uint64_t va_base_alignment, uint64_t va_base_required,
uint64_t *va_base_allocated, amdgpu_va_handle *va_range_handle,
uint64_t flags) TAIL;
PROC int ac_drm_va_range_free(amdgpu_va_handle va_range_handle) TAIL;
PROC int ac_drm_va_range_query(ac_drm_device *dev, enum amdgpu_gpu_va_range type, uint64_t *start,
MESAPROC int ac_drm_va_range_free(amdgpu_va_handle va_range_handle) TAIL;
MESAPROC int ac_drm_va_range_query(ac_drm_device *dev, enum amdgpu_gpu_va_range type, uint64_t *start,
uint64_t *end) TAIL;
PROC int ac_drm_create_userqueue(ac_drm_device *dev, uint32_t ip_type, uint32_t doorbell_handle,
MESAPROC int ac_drm_create_userqueue(ac_drm_device *dev, uint32_t ip_type, uint32_t doorbell_handle,
uint32_t doorbell_offset, uint64_t queue_va, uint64_t queue_size,
uint64_t wptr_va, uint64_t rptr_va, void *mqd_in, uint32_t flags,
uint32_t *queue_id) TAIL;
PROC int ac_drm_free_userqueue(ac_drm_device *dev, uint32_t queue_id) TAIL;
PROC int ac_drm_userq_signal(ac_drm_device *dev, struct drm_amdgpu_userq_signal *signal_data) TAIL;
PROC int ac_drm_userq_wait(ac_drm_device *dev, struct drm_amdgpu_userq_wait *wait_data) TAIL;
MESAPROC int ac_drm_free_userqueue(ac_drm_device *dev, uint32_t queue_id) TAIL;
MESAPROC int ac_drm_userq_signal(ac_drm_device *dev, struct drm_amdgpu_userq_signal *signal_data) TAIL;
MESAPROC int ac_drm_userq_wait(ac_drm_device *dev, struct drm_amdgpu_userq_wait *wait_data) TAIL;
PROC int ac_drm_query_pci_bus_info(ac_drm_device *dev, struct radeon_info *info) TAIL;
PROC void ac_drm_query_has_vm_always_valid(ac_drm_device *dev, struct radeon_info *info) TAILV;
MESAPROC int ac_drm_query_pci_bus_info(ac_drm_device *dev, struct radeon_info *info) TAIL;
MESAPROC void ac_drm_query_has_vm_always_valid(ac_drm_device *dev, struct radeon_info *info) TAILV;
#ifdef __cplusplus
}

90
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -24,15 +24,13 @@
#include "ac_sqtt.h"
#include "ac_spm.h"
#include "si_perfetto.h"
#ifndef HAVE_GFX_COMPUTE
#define __U_STUB__
#endif
#include "u_stub.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "util/u_stub_gfx_compute.h"
#undef MESA_LOG_TAG
#define MESA_LOG_TAG "radeonsi"
@ -1392,10 +1390,10 @@ void si_blitter_end(struct si_context *sctx);
void si_init_blit_functions(struct si_context *sctx);
void gfx6_decompress_textures(struct si_context *sctx, unsigned shader_mask);
void gfx11_decompress_textures(struct si_context *sctx, unsigned shader_mask);
PROC void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
MESAPROC void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *tex, unsigned planes,
unsigned level, unsigned first_layer, unsigned last_layer,
bool need_fmask_expand) TAILV;
PROC void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
MESAPROC void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box) TAILV;
@ -1403,9 +1401,9 @@ void si_gfx_copy_image(struct si_context *sctx, struct pipe_resource *dst,
unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src, unsigned src_level,
const struct pipe_box *src_box);
PROC void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
MESAPROC void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
void si_flush_implicit_resources(struct si_context *sctx);
PROC void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) TAILV;
MESAPROC void si_gfx_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) TAILV;
/* si_nir_optim.c */
bool si_nir_is_output_const_if_tex_is_const(struct nir_shader *shader, float *in, float *out, int *texunit);
@ -1487,43 +1485,43 @@ bool si_setup_compute_scratch_buffer(struct si_screen *screen,
void si_destroy_compute(struct si_compute *program);
/* si_compute_blit.c */
PROC bool si_should_blit_clamp_to_edge(const struct pipe_blit_info *info, unsigned coord_mask) TAILB;
PROC void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
MESAPROC bool si_should_blit_clamp_to_edge(const struct pipe_blit_info *info, unsigned coord_mask) TAILB;
MESAPROC void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
void *shader, unsigned num_buffers,
const struct pipe_shader_buffer *buffers,
unsigned writeable_bitmask, bool render_condition_enable) TAILV;
PROC bool si_compute_clear_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
MESAPROC bool si_compute_clear_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
unsigned dst_offset, struct pipe_resource *src,
unsigned src_offset, unsigned size,
const uint32_t *clear_value, unsigned clear_value_size,
unsigned dwords_per_thread, bool render_condition_enable,
bool fail_if_slow) TAILB;
PROC void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
MESAPROC void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
unsigned dst_offset, unsigned size, uint32_t clear_value,
uint32_t writebitmask, bool render_condition_enable) TAILV;
PROC void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
MESAPROC void si_compute_shorten_ubyte_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
uint64_t dst_offset, uint64_t src_offset, unsigned size,
bool render_condition_enable) TAILV;
PROC void si_compute_clear_image_dcc_single(struct si_context *sctx, struct si_texture *tex,
MESAPROC void si_compute_clear_image_dcc_single(struct si_context *sctx, struct si_texture *tex,
unsigned level, enum pipe_format format,
const union pipe_color_union *color,
bool render_condition_enable) TAILV;
PROC void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
PROC void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
MESAPROC void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) TAILV;
MESAPROC void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
bool render_condition_enable) TAILV;
PROC void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex) TAILV;
PROC bool si_compute_clear_image(struct si_context *sctx, struct pipe_resource *tex,
MESAPROC void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex) TAILV;
MESAPROC bool si_compute_clear_image(struct si_context *sctx, struct pipe_resource *tex,
enum pipe_format format, unsigned level, const struct pipe_box *box,
const union pipe_color_union *color, bool render_condition_enable,
bool fail_if_slow) TAILB;
PROC bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
MESAPROC bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
struct pipe_resource *src, unsigned src_level, unsigned dstx,
unsigned dsty, unsigned dstz, const struct pipe_box *src_box,
bool fail_if_slow) TAILB;
PROC bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
MESAPROC bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
const union pipe_color_union *clear_color, unsigned dst_access,
unsigned src_access, bool fail_if_slow) TAILB;
PROC void si_init_compute_blit_functions(struct si_context *sctx) TAILV;
MESAPROC void si_init_compute_blit_functions(struct si_context *sctx) TAILV;
/* si_cp_dma.c */
void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
@ -1540,7 +1538,7 @@ void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned
struct si_resource *src, unsigned src_offset);
/* si_cp_reg_shadowing.c */
PROC bool si_init_cp_reg_shadowing(struct si_context *sctx) TAILBT;
MESAPROC bool si_init_cp_reg_shadowing(struct si_context *sctx) TAILBT;
/* si_cp_utils.c */
void si_cp_release_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
@ -1566,11 +1564,11 @@ void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved);
void si_print_current_ib(struct si_context *sctx, FILE *f);
/* si_debug_gfx_compute.c */
PROC bool si_replace_shader(unsigned num, struct si_shader_binary *binary) TAILB;
PROC void si_dump_annotated_shaders(struct si_context *sctx, FILE *f) TAILV;
PROC void si_log_draw_state(struct si_context *sctx, struct u_log_context *log) TAILV;
PROC void si_gather_context_rolls(struct si_context *sctx) TAILV;
PROC void si_log_compute_state(struct si_context *sctx, struct u_log_context *log) TAILV;
MESAPROC bool si_replace_shader(unsigned num, struct si_shader_binary *binary) TAILB;
MESAPROC void si_dump_annotated_shaders(struct si_context *sctx, FILE *f) TAILV;
MESAPROC void si_log_draw_state(struct si_context *sctx, struct u_log_context *log) TAILV;
MESAPROC void si_gather_context_rolls(struct si_context *sctx) TAILV;
MESAPROC void si_log_compute_state(struct si_context *sctx, struct u_log_context *log) TAILV;
/* si_fence.c */
void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
@ -1613,7 +1611,7 @@ unsigned si_end_counter(struct si_screen *sscreen, unsigned type, uint64_t begin
/* si_compute.c */
void *si_create_compute_state_for_nir(struct pipe_context *ctx, nir_shader *nir,
enum mesa_shader_stage stage);
PROC void si_init_compute_functions(struct si_context *sctx) TAILV;
MESAPROC void si_init_compute_functions(struct si_context *sctx) TAILV;
/* si_pipe.c */
struct ac_llvm_compiler *si_create_llvm_compiler(struct si_screen *sscreen);
@ -1641,7 +1639,7 @@ void si_resume_queries(struct si_context *sctx);
/* si_shaderlib_nir.c */
PROC void *si_create_shader_state(struct si_context *sctx, struct nir_shader *nir) TAILPTR;
MESAPROC void *si_create_shader_state(struct si_context *sctx, struct nir_shader *nir) TAILPTR;
void *si_create_dcc_retile_cs(struct si_context *sctx, const struct radeon_surf *surf);
void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
void *si_create_passthrough_tcs(struct si_context *sctx);
@ -1651,22 +1649,22 @@ void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
void *si_create_ubyte_to_ushort_compute_shader(struct si_context *sctx);
void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
void *si_create_fmask_expand_cs(struct si_context *sctx, unsigned num_samples, bool is_array);
PROC void *si_create_query_result_cs(struct si_context *sctx) TAILPTR;
PROC void *gfx11_create_sh_query_result_cs(struct si_context *sctx) TAILPTR;
MESAPROC void *si_create_query_result_cs(struct si_context *sctx) TAILPTR;
MESAPROC void *gfx11_create_sh_query_result_cs(struct si_context *sctx) TAILPTR;
/* gfx11_query.c */
void si_gfx11_init_query(struct si_context *sctx);
void si_gfx11_destroy_query(struct si_context *sctx);
/* si_test_image_copy_region.c */
PROC void si_test_image_copy_region(struct si_screen *sscreen) TAILV;
PROC void si_test_blit(struct si_screen *sscreen, unsigned test_flags) TAILV;
MESAPROC void si_test_image_copy_region(struct si_screen *sscreen) TAILV;
MESAPROC void si_test_blit(struct si_screen *sscreen, unsigned test_flags) TAILV;
/* si_test_dma_perf.c */
PROC void si_test_dma_perf(struct si_screen *sscreen) TAILV;
PROC void si_test_mem_perf(struct si_screen *sscreen) TAILV;
PROC void si_test_clear_buffer(struct si_screen *sscreen) TAILV;
PROC void si_test_copy_buffer(struct si_screen *sscreen) TAILV;
MESAPROC void si_test_dma_perf(struct si_screen *sscreen) TAILV;
MESAPROC void si_test_mem_perf(struct si_screen *sscreen) TAILV;
MESAPROC void si_test_clear_buffer(struct si_screen *sscreen) TAILV;
MESAPROC void si_test_copy_buffer(struct si_screen *sscreen) TAILV;
/* si_state_viewport.c */
void si_update_vs_viewport_state(struct si_context *ctx);
@ -1708,24 +1706,24 @@ void
si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_event_type api_type,
uint32_t x, uint32_t y, uint32_t z);
PROC void
MESAPROC void
si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
enum rgp_sqtt_marker_user_event_type type,
const char *str, int len) TAILV;
PROC void
MESAPROC void
si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs) TAILV;
PROC void
MESAPROC void
si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags) TAILV;
PROC bool si_init_sqtt(struct si_context *sctx) TAILB;
PROC void si_destroy_sqtt(struct si_context *sctx) TAILV;
PROC void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs) TAILV;
MESAPROC bool si_init_sqtt(struct si_context *sctx) TAILB;
MESAPROC void si_destroy_sqtt(struct si_context *sctx) TAILV;
MESAPROC void si_handle_sqtt(struct si_context *sctx, struct radeon_cmdbuf *rcs) TAILV;
/* si_mesh_shader.c */
PROC void si_init_task_mesh_shader_functions(struct si_context *sctx) TAILV;
MESAPROC void si_init_task_mesh_shader_functions(struct si_context *sctx) TAILV;
/* si_nir_mediump.c */
PROC void si_nir_lower_mediump_io_default(nir_shader *nir) TAILV;
PROC void si_nir_lower_mediump_io_option(nir_shader *nir) TAILV;
MESAPROC void si_nir_lower_mediump_io_default(nir_shader *nir) TAILV;
MESAPROC void si_nir_lower_mediump_io_option(nir_shader *nir) TAILV;
/*
* common helpers

14
src/gallium/drivers/radeonsi/si_shader.h
View file

@ -119,15 +119,13 @@
#include "util/u_queue.h"
#include "si_pm4.h"
#include "si_shader_info.h"
#ifndef HAVE_GFX_COMPUTE
#define __U_STUB__
#endif
#include "u_stub.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "util/u_stub_gfx_compute.h"
struct nir_shader;
struct nir_instr;
@ -906,7 +904,7 @@ void si_nir_gather_info(struct si_screen *sscreen, struct nir_shader *nir,
/* si_shader_nir.c */
void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool has_array_temps);
void si_nir_late_opts(struct nir_shader *nir);
PROC void si_finalize_nir(struct pipe_screen *screen, struct nir_shader *nir,
MESAPROC void si_finalize_nir(struct pipe_screen *screen, struct nir_shader *nir,
bool optimize) TAILV;
/* si_state_shaders.cpp */
@ -926,11 +924,11 @@ int si_shader_binary_upload_at(struct si_screen *sscreen, struct si_shader *shad
uint64_t scratch_va, int64_t bo_offset);
void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shader *shader,
struct util_debug_callback *debug);
PROC void si_shader_binary_clean(struct si_shader_binary *binary) TAILV;
MESAPROC void si_shader_binary_clean(struct si_shader_binary *binary) TAILV;
const char *si_get_shader_name(const struct si_shader *shader);
PROC bool si_can_dump_shader(struct si_screen *sscreen, mesa_shader_stage stage,
MESAPROC bool si_can_dump_shader(struct si_screen *sscreen, mesa_shader_stage stage,
enum si_shader_dump_type dump_type) TAILB;
PROC void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
MESAPROC void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
struct util_debug_callback *debug, FILE *f, bool check_debug_option) TAILV;
/* Inline helpers. */

19
src/gallium/drivers/radeonsi/si_state.h
View file

@ -17,10 +17,7 @@
extern "C" {
#endif
#ifndef HAVE_GFX_COMPUTE
#define __U_STUB__
#endif
#include "u_stub.h"
#include "util/u_stub_gfx_compute.h"
#define SI_NUM_GRAPHICS_SHADERS (MESA_SHADER_FRAGMENT + 1)
#define SI_NUM_SHADERS (MESA_SHADER_MESH + 1)
@ -487,27 +484,27 @@ bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_bla
void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_blake3_cache_key[BLAKE3_KEY_LEN],
struct si_shader *shader, bool insert_into_disk_cache);
bool si_shader_mem_ordered(struct si_shader *shader);
PROC void si_init_screen_live_shader_cache(struct si_screen *sscreen) TAILV;
MESAPROC void si_init_screen_live_shader_cache(struct si_screen *sscreen) TAILV;
void si_init_shader_functions(struct si_context *sctx);
PROC bool si_init_shader_cache(struct si_screen *sscreen) TAILBT;
PROC void si_destroy_shader_cache(struct si_screen *sscreen) TAILV;
MESAPROC bool si_init_shader_cache(struct si_screen *sscreen) TAILBT;
MESAPROC void si_destroy_shader_cache(struct si_screen *sscreen) TAILV;
void si_schedule_initial_compile(struct si_context *sctx, mesa_shader_stage stage,
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state *compiler_ctx_state, void *job,
util_queue_execute_func execute);
int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state);
PROC void si_vs_key_update_inputs(struct si_context *sctx) TAILV;
MESAPROC void si_vs_key_update_inputs(struct si_context *sctx) TAILV;
void si_update_ps_inputs_read_or_disabled(struct si_context *sctx);
void si_update_vrs_flat_shading(struct si_context *sctx);
unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key,
bool return_unknown);
unsigned si_get_num_vertices_per_output_prim(struct si_shader *shader);
PROC bool si_update_ngg(struct si_context *sctx) TAILB;
MESAPROC bool si_update_ngg(struct si_context *sctx) TAILB;
void si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context *sctx);
void si_ps_key_update_framebuffer_blend_dsa_rasterizer(struct si_context *sctx);
void si_ps_key_update_rasterizer(struct si_context *sctx);
void si_ps_key_update_dsa(struct si_context *sctx);
PROC void si_ps_key_update_sample_shading(struct si_context *sctx) TAILV;
MESAPROC void si_ps_key_update_sample_shading(struct si_context *sctx) TAILV;
void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx);
void si_init_tess_factor_ring(struct si_context *sctx);
bool si_update_gs_ring_buffers(struct si_context *sctx);
@ -522,7 +519,7 @@ void si_cp_dma_prefetch(struct radeon_cmdbuf *cs,
enum amd_gfx_level gfx_level,
struct pipe_resource *buf,
unsigned offset, unsigned size);
PROC void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
MESAPROC void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
const struct pipe_vertex_buffer *vb, unsigned element_index,
uint32_t *out) TAILV;
void si_emit_buffered_compute_sh_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);

12
src/amd/common/u_stub.h → src/util/u_stub.h
View file

@ -14,19 +14,24 @@
*
*/
#undef PROC
#undef MESAPROC
#undef TAIL
#undef TAILZ
#undef TAILV
#undef TAILB
#undef TAILBT
#undef TAILPTR
#ifdef __U_STUB__
#define PROC static inline
#define MESAPROC static inline
#define TAIL \
{ \
return -1; \
}
#define TAILZ \
{ \
return 0; \
}
#define TAILV \
{ \
}
@ -43,8 +48,9 @@
return true; \
}
#else
#define PROC
#define MESAPROC
#define TAIL
#define TAILZ
#define TAILV
#define TAILB
#define TAILBT

10
src/util/u_stub_gfx_compute.h Normal file
View file

@ -0,0 +1,10 @@
/*
* Copyright 2026 Advanced Micro Devices, Inc.
*
* SPDX-License-Identifier: MIT
*/
#ifndef HAVE_GFX_COMPUTE
#define __U_STUB__
#endif
#include "util/u_stub.h"