From f9d57207a365a896a771e3b3b62351749fbd99c6 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 22 Apr 2021 15:02:20 -0700
Subject: [PATCH] ci/radeonsi: Mark a glx_arb_sync_control/timing flake.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

I've seen this one happen at least twice today. Log shows something like:

    Wallclock time between MSCs 16982.888889us does not match
    glXGetMscRateOML 16668.071966us

or

    Wallclock time between MSCs 16500.333333us does not match
    glXGetMscRateOML 16668.071966us

Incidentally, both runs I've looked into had one run too fast and one run
too slow.

Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10414>
---
 .../drivers/radeonsi/ci/piglit-radeonsi-stoney-flakes.txt        | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 src/gallium/drivers/radeonsi/ci/piglit-radeonsi-stoney-flakes.txt

diff --git a/src/gallium/drivers/radeonsi/ci/piglit-radeonsi-stoney-flakes.txt b/src/gallium/drivers/radeonsi/ci/piglit-radeonsi-stoney-flakes.txt
new file mode 100644
index 00000000000..8c103bc5162
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/ci/piglit-radeonsi-stoney-flakes.txt
@@ -0,0 +1 @@
+glx@glx_arb_sync_control@timing -fullscreen -divisor 2