diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index b4f253f4c79..7dd1f431527 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -229,7 +229,6 @@ struct fd_dev_info {
       struct {
          uint32_t RB_DBG_ECO_CNTL;
          uint32_t RB_DBG_ECO_CNTL_blit;
-         uint32_t HLSQ_DBG_ECO_CNTL;
          uint32_t RB_RBP_CNTL;
          uint32_t VPC_DBG_ECO_CNTL;
          uint32_t UCHE_UNKNOWN_0E12;
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 5bfc61ad023..ec6efb29268 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -470,7 +470,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0,
             RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x10000000,
@@ -484,6 +483,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -507,7 +507,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x00080000,
             RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -521,6 +520,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000430],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0x00080000],
         ],
     ))
 
@@ -539,7 +539,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -553,6 +552,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -572,7 +572,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -586,6 +585,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x03000000],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -606,7 +606,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x05100000,
-            HLSQ_DBG_ECO_CNTL = 0x00080000,
             RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x10000001
@@ -620,6 +619,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0x00080000],
         ],
     ))
 
@@ -640,7 +640,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -654,6 +653,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000420],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -674,7 +674,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -688,6 +687,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -707,7 +707,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -722,6 +721,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -747,7 +747,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -761,6 +760,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x00000006],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -780,7 +780,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -794,6 +793,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x01000000],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -813,7 +813,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -827,6 +826,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x6],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -847,7 +847,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x100000,
             RB_DBG_ECO_CNTL_blit = 0x00100000,  # ???
-            HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x2000400,
             UCHE_UNKNOWN_0E12 = 0x00000001
@@ -862,6 +861,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0x1200000],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0],
         ],
     ))
 
@@ -896,7 +896,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x100000,
             RB_DBG_ECO_CNTL_blit = 0x100000,
-            HLSQ_DBG_ECO_CNTL = 0x02000000,
             RB_RBP_CNTL = 0x1,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x1,
@@ -910,6 +909,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400],
             [A6XXRegs.REG_A6XX_SP_DBG_ECO_CNTL, 0],
             [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084],
+            [A6XXRegs.REG_A6XX_HLSQ_DBG_ECO_CNTL, 0x02000000],
         ],
     ))
 
@@ -1073,7 +1073,6 @@ a730_raw_magic_regs = [
 a740_magic_regs = dict(
         RB_DBG_ECO_CNTL = 0x00000000,
         RB_DBG_ECO_CNTL_blit = 0x00000000,  # is it even needed?
-        # HLSQ_DBG_ECO_CNTL = 0x0,
         RB_RBP_CNTL = 0x0,
         VPC_DBG_ECO_CNTL = 0x02000000,
         UCHE_UNKNOWN_0E12 = 0x00000000,
@@ -1322,7 +1321,6 @@ add_gpus([
         magic_regs = dict(
             RB_DBG_ECO_CNTL = 0x00000001,
             RB_DBG_ECO_CNTL_blit = 0x00000000,  # is it even needed?
-            # HLSQ_DBG_ECO_CNTL = 0x0,
             RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000000,
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index 85cfbaa814b..661b6d3f730 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -1972,10 +1972,6 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
 
    tu_cs_emit_write_reg(cs, REG_A6XX_VPC_DBG_ECO_CNTL,
                         phys_dev->info->a6xx.magic.VPC_DBG_ECO_CNTL);
-   if (CHIP == A6XX) {
-      tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_DBG_ECO_CNTL,
-                           phys_dev->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
-   }
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_GFX_USIZE, 0); // 2 on a740 ???
    tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_PS_ROTATION_CNTL, 0);
    if (CHIP == A6XX)
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
index ec15596b8c8..7e9514cffae 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
@@ -877,9 +877,6 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
    }
 
    ncrb.add(VPC_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.VPC_DBG_ECO_CNTL));
-   if (CHIP == A6XX)
-      ncrb.add(HLSQ_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL));
-
    ncrb.add(UCHE_UNKNOWN_0E12(CHIP, .dword = screen->info->a6xx.magic.UCHE_UNKNOWN_0E12));
 
    if (CHIP == A6XX) {