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r600g: lower number of driver const buffers
I'm going to want a driver constant buffer for tess to coordinate LDS storage, so before I go tackling that I decided to merge the clip/samplepos and texture info buffers into one. So I can steal the spare one. This creates a single constant buffer between the two, with clip/samplepos taking up a reserved 128 bytes at the start. Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
0337a9b2af
commit
f9caabe8f1
3 changed files with 131 additions and 70 deletions
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@ -63,13 +63,15 @@
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#define R600_TRACE_CS_DWORDS 7
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#define R600_MAX_USER_CONST_BUFFERS 13
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#define R600_MAX_DRIVER_CONST_BUFFERS 3
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#define R600_MAX_DRIVER_CONST_BUFFERS 2
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#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
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/* start driver buffers after user buffers */
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#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
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#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
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#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
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#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
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#define R600_UCP_SIZE (4*4*8)
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#define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
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#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
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/* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
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* of 16 const buffers.
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* UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
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@ -77,8 +79,6 @@
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* In order to support d3d 11 mandated minimum of 15 user const buffers
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* we'd have to squash all use cases into one driver buffer.
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*/
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#define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
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#define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
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#ifdef PIPE_ARCH_BIG_ENDIAN
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@ -356,11 +356,15 @@ struct r600_textures_info {
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struct r600_samplerview_state views;
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struct r600_sampler_states states;
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bool is_array_sampler[NUM_TEX_UNITS];
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};
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/* cube array txq workaround */
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uint32_t *txq_constants;
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/* buffer related workarounds */
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uint32_t *buffer_constants;
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struct r600_shader_driver_constants_info {
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/* currently 128 bytes for UCP/samplepos + sampler buffer constants */
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uint32_t *constants;
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uint32_t alloc_size;
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bool vs_ucp_dirty;
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bool texture_const_dirty;
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bool ps_sample_pos_dirty;
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};
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struct r600_constbuf_state
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@ -472,6 +476,9 @@ struct r600_context {
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struct r600_gs_rings_state gs_rings;
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struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
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struct r600_textures_info samplers[PIPE_SHADER_TYPES];
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struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
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/** Vertex buffers for fetch shaders */
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struct r600_vertexbuf_state vertex_buffer_state;
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/** Vertex buffers for compute shaders */
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@ -498,6 +505,7 @@ struct r600_context {
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void *sb_context;
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struct r600_isa *isa;
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float sample_positions[4 * 16];
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};
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static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
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@ -60,6 +60,7 @@ issued in the w slot as well.
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The compiler must issue the source argument to slots z, y, and x
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*/
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#define R600_SHADER_BUFFER_INFO_SEL (512 + R600_BUFFER_INFO_OFFSET / 16)
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static int r600_shader_from_tgsi(struct r600_context *rctx,
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struct r600_pipe_shader *pipeshader,
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union r600_shader_key key);
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@ -947,7 +948,7 @@ static int load_sample_position(struct r600_shader_ctx *ctx, struct r600_shader_
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memset(&vtx, 0, sizeof(struct r600_bytecode_vtx));
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vtx.op = FETCH_OP_VFETCH;
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vtx.buffer_id = R600_SAMPLE_POSITIONS_CONST_BUFFER;
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vtx.buffer_id = R600_BUFFER_INFO_CONST_BUFFER;
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vtx.fetch_type = SQ_VTX_FETCH_NO_INDEX_OFFSET;
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if (sample_id == NULL) {
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vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
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@ -2307,7 +2308,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
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alu.src[0].chan = j;
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alu.src[1].sel = 512 + i;
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alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
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alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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alu.src[1].chan = j;
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alu.dst.sel = clipdist_temp[oreg];
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@ -5499,7 +5500,8 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
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alu.src[0].sel = vtx.dst_gpr;
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alu.src[0].chan = i;
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alu.src[1].sel = 512 + (id * 2);
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alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL;
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alu.src[1].sel += (id * 2);
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alu.src[1].chan = i % 4;
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alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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@ -5521,7 +5523,7 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_l
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alu.src[0].sel = vtx.dst_gpr;
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alu.src[0].chan = 3;
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alu.src[1].sel = 512 + (id * 2) + 1;
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alu.src[1].sel = R600_SHADER_BUFFER_INFO_SEL + (id * 2) + 1;
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alu.src[1].chan = 0;
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alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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@ -5542,14 +5544,14 @@ static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
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if (ctx->bc->chip_class >= EVERGREEN) {
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/* channel 0 or 2 of each word */
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alu.src[0].sel = 512 + (id / 2);
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alu.src[0].sel += (id / 2);
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alu.src[0].chan = (id % 2) * 2;
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} else {
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/* r600 we have them at channel 2 of the second dword */
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alu.src[0].sel = 512 + (id * 2) + 1;
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alu.src[0].sel += (id * 2) + 1;
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alu.src[0].chan = 1;
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}
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alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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@ -6207,13 +6209,14 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.op = ALU_OP1_MOV;
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alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
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if (ctx->bc->chip_class >= EVERGREEN) {
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/* channel 1 or 3 of each word */
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alu.src[0].sel = 512 + (id / 2);
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alu.src[0].sel += (id / 2);
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alu.src[0].chan = ((id % 2) * 2) + 1;
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} else {
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/* r600 we have them at channel 2 of the second dword */
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alu.src[0].sel = 512 + (id * 2) + 1;
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alu.src[0].sel += (id * 2) + 1;
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alu.src[0].chan = 2;
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}
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alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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@ -240,17 +240,10 @@ static void r600_set_clip_state(struct pipe_context *ctx,
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const struct pipe_clip_state *state)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct pipe_constant_buffer cb;
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rctx->clip_state.state = *state;
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r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
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cb.buffer = NULL;
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cb.user_buffer = state->ucp;
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cb.buffer_offset = 0;
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cb.buffer_size = 4*4*8;
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ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
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pipe_resource_reference(&cb.buffer, NULL);
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rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
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}
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static void r600_set_stencil_ref(struct pipe_context *ctx,
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@ -1053,6 +1046,74 @@ static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask
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r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
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}
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static void r600_update_driver_const_buffers(struct r600_context *rctx)
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{
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int sh, size;;
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void *ptr;
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struct pipe_constant_buffer cb;
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for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
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struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
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if (!info->vs_ucp_dirty &&
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!info->texture_const_dirty &&
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!info->ps_sample_pos_dirty)
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continue;
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ptr = info->constants;
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size = info->alloc_size;
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if (info->vs_ucp_dirty) {
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assert(sh == PIPE_SHADER_VERTEX);
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if (!size) {
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ptr = rctx->clip_state.state.ucp;
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size = R600_UCP_SIZE;
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} else {
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memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
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}
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info->vs_ucp_dirty = false;
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}
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if (info->ps_sample_pos_dirty) {
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assert(sh == PIPE_SHADER_FRAGMENT);
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if (!size) {
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ptr = rctx->sample_positions;
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size = R600_UCP_SIZE;
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} else {
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memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
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}
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info->ps_sample_pos_dirty = false;
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}
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if (info->texture_const_dirty) {
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assert (ptr);
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assert (size);
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if (sh == PIPE_SHADER_VERTEX)
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memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
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if (sh == PIPE_SHADER_FRAGMENT)
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memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
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}
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info->texture_const_dirty = false;
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cb.buffer = NULL;
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cb.user_buffer = ptr;
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cb.buffer_offset = 0;
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cb.buffer_size = size;
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rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
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pipe_resource_reference(&cb.buffer, NULL);
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}
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}
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static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
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int array_size, uint32_t *base_offset)
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{
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struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
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if (array_size + R600_UCP_SIZE > info->alloc_size) {
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info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
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info->alloc_size = array_size + R600_UCP_SIZE;
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}
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memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
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info->texture_const_dirty = true;
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*base_offset = R600_UCP_SIZE;
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return info->constants;
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}
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/*
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* On r600/700 hw we don't have vertex fetch swizzle, though TBO
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* doesn't require full swizzles it does need masking and setting alpha
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@ -1067,9 +1128,9 @@ static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_ty
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struct r600_textures_info *samplers = &rctx->samplers[shader_type];
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int bits;
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uint32_t array_size;
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struct pipe_constant_buffer cb;
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int i, j;
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uint32_t *constants;
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uint32_t base_offset;
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if (!samplers->views.dirty_buffer_constants)
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return;
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@ -1077,38 +1138,33 @@ static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_ty
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bits = util_last_bit(samplers->views.enabled_mask);
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array_size = bits * 8 * sizeof(uint32_t) * 4;
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samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
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memset(samplers->buffer_constants, 0, array_size);
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constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
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for (i = 0; i < bits; i++) {
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if (samplers->views.enabled_mask & (1 << i)) {
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int offset = i * 8;
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int offset = (base_offset / 4) + i * 8;
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const struct util_format_description *desc;
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desc = util_format_description(samplers->views.views[i]->base.format);
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for (j = 0; j < 4; j++)
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if (j < desc->nr_channels)
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samplers->buffer_constants[offset+j] = 0xffffffff;
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constants[offset+j] = 0xffffffff;
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else
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samplers->buffer_constants[offset+j] = 0x0;
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constants[offset+j] = 0x0;
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if (desc->nr_channels < 4) {
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if (desc->channel[0].pure_integer)
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samplers->buffer_constants[offset+4] = 1;
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constants[offset+4] = 1;
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else
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samplers->buffer_constants[offset+4] = fui(1.0);
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constants[offset+4] = fui(1.0);
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} else
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samplers->buffer_constants[offset + 4] = 0;
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constants[offset + 4] = 0;
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samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
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samplers->buffer_constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
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constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
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constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
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}
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}
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cb.buffer = NULL;
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cb.user_buffer = samplers->buffer_constants;
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cb.buffer_offset = 0;
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cb.buffer_size = array_size;
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rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
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pipe_resource_reference(&cb.buffer, NULL);
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}
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/* On evergreen we store two values
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@ -1120,9 +1176,9 @@ static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type
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struct r600_textures_info *samplers = &rctx->samplers[shader_type];
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int bits;
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uint32_t array_size;
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struct pipe_constant_buffer cb;
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int i;
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uint32_t *constants;
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uint32_t base_offset;
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if (!samplers->views.dirty_buffer_constants)
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return;
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@ -1130,45 +1186,37 @@ static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type
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bits = util_last_bit(samplers->views.enabled_mask);
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array_size = bits * 2 * sizeof(uint32_t) * 4;
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samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
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memset(samplers->buffer_constants, 0, array_size);
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constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
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&base_offset);
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for (i = 0; i < bits; i++) {
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if (samplers->views.enabled_mask & (1 << i)) {
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uint32_t offset = i * 2;
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samplers->buffer_constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
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samplers->buffer_constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
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uint32_t offset = (base_offset / 4) + i * 2;
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constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
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constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
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}
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}
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cb.buffer = NULL;
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cb.user_buffer = samplers->buffer_constants;
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cb.buffer_offset = 0;
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cb.buffer_size = array_size;
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rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
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pipe_resource_reference(&cb.buffer, NULL);
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}
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/* set sample xy locations as array of fragment shader constants */
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void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
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{
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struct pipe_constant_buffer constbuf = {0};
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float values[4*16] = {0.0f};
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int i;
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struct pipe_context *ctx = &rctx->b.b;
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assert(rctx->framebuffer.nr_samples <= Elements(values)/4);
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assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
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assert(rctx->framebuffer.nr_samples <= Elements(rctx->sample_positions)/4);
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memset(rctx->sample_positions, 0, 4 * 4 * 16);
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for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
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ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &values[4*i]);
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ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
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||||
/* Also fill in center-zeroed positions used for interpolateAtSample */
|
||||
values[4*i + 2] = values[4*i + 0] - 0.5f;
|
||||
values[4*i + 3] = values[4*i + 1] - 0.5f;
|
||||
rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
|
||||
rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
|
||||
}
|
||||
|
||||
constbuf.user_buffer = values;
|
||||
constbuf.buffer_size = rctx->framebuffer.nr_samples * 4 * 4;
|
||||
ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
|
||||
R600_SAMPLE_POSITIONS_CONST_BUFFER, &constbuf);
|
||||
pipe_resource_reference(&constbuf.buffer, NULL);
|
||||
rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
|
||||
}
|
||||
|
||||
static void update_shader_atom(struct pipe_context *ctx,
|
||||
|
|
@ -1387,6 +1435,8 @@ static bool r600_update_derived_state(struct r600_context *rctx)
|
|||
}
|
||||
}
|
||||
|
||||
r600_update_driver_const_buffers(rctx);
|
||||
|
||||
if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
|
||||
if (!r600_adjust_gprs(rctx)) {
|
||||
/* discard rendering */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue