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radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos
just deduplicate the code Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
This commit is contained in:
Marek Olšák
Marge Bot
parent
ec60526035
commit
f9b527a9a5
6 changed files with 62 additions and 154 deletions
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@ -387,7 +387,6 @@ static void gfx10_sh_query_get_result_resource(struct si_context *sctx, struct s
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}
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sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, false, &constant_buffer);
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo, 0x6);
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if (wait) {
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uint64_t va;
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@ -403,8 +402,9 @@ static void gfx10_sh_query_get_result_resource(struct si_context *sctx, struct s
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si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x00000001, 0x00000001, 0);
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}
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si_launch_grid_internal((struct si_context *)&sctx->b, &grid, sctx->sh_query_result_shader,
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SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_AFTER);
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si_launch_grid_internal_ssbos(sctx, &grid, sctx->sh_query_result_shader,
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SI_OP_SYNC_PS_BEFORE | SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
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3, ssbo, 0x6);
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if (qbuf == query->last)
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break;
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@ -116,6 +116,47 @@ void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *inf
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}
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}
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void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
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void *shader, unsigned flags, enum si_coherency coher,
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unsigned num_buffers, const struct pipe_shader_buffer *buffers,
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unsigned writeable_bitmask)
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{
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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/* Save states. */
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struct pipe_shader_buffer saved_sb[3] = {};
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assert(num_buffers <= ARRAY_SIZE(saved_sb));
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, num_buffers, saved_sb);
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unsigned saved_writable_mask = 0;
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for (unsigned i = 0; i < num_buffers; i++) {
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(i)))
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saved_writable_mask |= 1 << i;
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}
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/* Bind buffers and launch compute. */
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_buffers, buffers,
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writeable_bitmask);
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si_launch_grid_internal(sctx, info, shader, flags);
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/* Do cache flushing at the end. */
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if (get_cache_policy(sctx, coher, 0) == L2_BYPASS) {
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if (flags & SI_OP_SYNC_AFTER)
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sctx->flags |= SI_CONTEXT_WB_L2;
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} else {
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while (writeable_bitmask)
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si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true;
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}
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/* Restore states. */
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_buffers, saved_sb,
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saved_writable_mask);
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for (int i = 0; i < num_buffers; i++)
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pipe_resource_reference(&saved_sb[i].buffer, NULL);
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}
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/**
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* Clear a buffer using read-modify-write with a 32-bit write bitmask.
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* The clear value has 32 bits.
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@ -125,25 +166,11 @@ void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *
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uint32_t clear_value, uint32_t writebitmask,
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unsigned flags, enum si_coherency coher)
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{
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struct pipe_context *ctx = &sctx->b;
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assert(dst_offset % 4 == 0);
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assert(size % 4 == 0);
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assert(dst->target != PIPE_BUFFER || dst_offset + size <= dst->width0);
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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/* Save states. */
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struct pipe_shader_buffer saved_sb = {};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb);
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unsigned saved_writable_mask = 0;
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(0)))
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saved_writable_mask |= 1 << 0;
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/* Use buffer_load_dwordx4 and buffer_store_dwordx4 per thread. */
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unsigned dwords_per_instruction = 4;
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unsigned wave_size = sctx->screen->compute_wave_size;
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@ -164,7 +191,6 @@ void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *
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sb.buffer = dst;
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sb.buffer_offset = dst_offset;
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sb.buffer_size = size;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &sb, 0x1);
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sctx->cs_user_data[0] = clear_value & writebitmask;
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sctx->cs_user_data[1] = ~writebitmask;
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@ -172,19 +198,8 @@ void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *
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if (!sctx->cs_clear_buffer_rmw)
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sctx->cs_clear_buffer_rmw = si_create_clear_buffer_rmw_cs(&sctx->b);
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si_launch_grid_internal(sctx, &info, sctx->cs_clear_buffer_rmw, flags);
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enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
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if (flags & SI_OP_SYNC_AFTER)
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sctx->flags |= cache_policy == L2_BYPASS ? SI_CONTEXT_WB_L2 : 0;
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if (cache_policy != L2_BYPASS)
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si_resource(dst)->TC_L2_dirty = true;
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/* Restore states. */
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb, saved_writable_mask);
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pipe_resource_reference(&saved_sb.buffer, NULL);
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si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_clear_buffer_rmw, flags, coher,
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1, &sb, 0x1);
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}
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static void si_compute_clear_12bytes_buffer(struct si_context *sctx, struct pipe_resource *dst,
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@ -198,24 +213,11 @@ static void si_compute_clear_12bytes_buffer(struct si_context *sctx, struct pipe
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assert(size % 4 == 0);
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unsigned size_12 = DIV_ROUND_UP(size, 12);
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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struct pipe_shader_buffer saved_sb = {0};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb);
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unsigned saved_writable_mask = 0;
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(0)))
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saved_writable_mask = 1;
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struct pipe_shader_buffer sb = {0};
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sb.buffer = dst;
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sb.buffer_offset = dst_offset;
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sb.buffer_size = size;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &sb, 0x1);
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memcpy(sctx->cs_user_data, clear_value, 12);
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struct pipe_grid_info info = {0};
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@ -231,10 +233,8 @@ static void si_compute_clear_12bytes_buffer(struct si_context *sctx, struct pipe
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info.grid[1] = 1;
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info.grid[2] = 1;
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si_launch_grid_internal(sctx, &info, sctx->cs_clear_12bytes_buffer, flags);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb, saved_writable_mask);
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pipe_resource_reference(&saved_sb.buffer, NULL);
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si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_clear_12bytes_buffer, flags, coher,
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1, &sb, 0x1);
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}
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static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_resource *dst,
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@ -243,8 +243,6 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_res
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const uint32_t *clear_value, unsigned clear_value_size,
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unsigned flags, enum si_coherency coher)
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{
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struct pipe_context *ctx = &sctx->b;
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assert(src_offset % 4 == 0);
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assert(dst_offset % 4 == 0);
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assert(size % 4 == 0);
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@ -252,20 +250,6 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_res
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assert(dst->target != PIPE_BUFFER || dst_offset + size <= dst->width0);
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assert(!src || src_offset + size <= src->width0);
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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/* Save states. */
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struct pipe_shader_buffer saved_sb[2] = {};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
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unsigned saved_writable_mask = 0;
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for (unsigned i = 0; i < (src ? 2 : 1); i++) {
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(i)))
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saved_writable_mask |= 1 << i;
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}
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/* The memory accesses are coalesced, meaning that the 1st instruction writes
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* the 1st contiguous block of data for the whole wave, the 2nd instruction
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* writes the 2nd contiguous block of data, etc.
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@ -300,14 +284,13 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_res
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sb[1].buffer_offset = src_offset;
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sb[1].buffer_size = size;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb, 0x1);
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if (!sctx->cs_copy_buffer) {
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sctx->cs_copy_buffer = si_create_dma_compute_shader(
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&sctx->b, SI_COMPUTE_COPY_DW_PER_THREAD, shader_dst_stream_policy, true);
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}
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si_launch_grid_internal(sctx, &info, sctx->cs_copy_buffer, flags);
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si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_copy_buffer, flags, coher,
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2, sb, 0x1);
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} else {
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assert(clear_value_size >= 4 && clear_value_size <= 16 &&
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util_is_power_of_two_or_zero(clear_value_size));
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@ -315,28 +298,14 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_res
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for (unsigned i = 0; i < 4; i++)
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sctx->cs_user_data[i] = clear_value[i % (clear_value_size / 4)];
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb, 0x1);
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if (!sctx->cs_clear_buffer) {
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sctx->cs_clear_buffer = si_create_dma_compute_shader(
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&sctx->b, SI_COMPUTE_CLEAR_DW_PER_THREAD, shader_dst_stream_policy, false);
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}
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si_launch_grid_internal(sctx, &info, sctx->cs_clear_buffer, flags);
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si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_clear_buffer, flags, coher,
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1, sb, 0x1);
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}
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enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, size);
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if (flags & SI_OP_SYNC_AFTER)
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sctx->flags |= cache_policy == L2_BYPASS ? SI_CONTEXT_WB_L2 : 0;
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if (cache_policy != L2_BYPASS)
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si_resource(dst)->TC_L2_dirty = true;
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/* Restore states. */
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb, saved_writable_mask);
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for (int i = 0; i < 2; i++)
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pipe_resource_reference(&saved_sb[i].buffer, NULL);
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}
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void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
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@ -653,19 +622,6 @@ void si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, u
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void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
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{
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struct pipe_context *ctx = &sctx->b;
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sctx->flags |= si_get_flush_flags(sctx, SI_COHERENCY_CB_META, L2_LRU);
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/* Save states. */
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struct pipe_shader_buffer saved_sb = {};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb);
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unsigned saved_writable_mask = 0;
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(0)))
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saved_writable_mask |= 1 << 0;
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/* Set the DCC buffer. */
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assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX);
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assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX);
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@ -676,7 +632,6 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
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sb.buffer = &tex->buffer.b.b;
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sb.buffer_offset = tex->surface.display_dcc_offset;
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sb.buffer_size = tex->buffer.bo_size - sb.buffer_offset;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &sb, 0x1);
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sctx->cs_user_data[0] = tex->surface.meta_offset - tex->surface.display_dcc_offset;
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sctx->cs_user_data[1] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) |
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@ -709,33 +664,17 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
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info.grid[1] = DIV_ROUND_UP(height, info.block[1]);
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info.grid[2] = 1;
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si_launch_grid_internal(sctx, &info, sctx->cs_dcc_retile, SI_OP_SYNC_BEFORE);
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si_launch_grid_internal_ssbos(sctx, &info, sctx->cs_dcc_retile, SI_OP_SYNC_BEFORE,
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SI_COHERENCY_CB_META, 1, &sb, 0x1);
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/* Don't flush caches. L2 will be flushed by the kernel fence. */
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/* Restore states. */
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb, saved_writable_mask);
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pipe_resource_reference(&saved_sb.buffer, NULL);
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}
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void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
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unsigned flags, enum si_coherency coher)
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{
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struct pipe_context *ctx = &sctx->b;
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struct si_texture *tex = (struct si_texture*)res;
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if (!(flags & SI_OP_SKIP_CACHE_INV_BEFORE))
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sctx->flags |= si_get_flush_flags(sctx, coher, SI_COMPUTE_DST_CACHE_POLICY);
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/* Save states. */
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struct pipe_shader_buffer saved_sb = {};
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si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb);
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unsigned saved_writable_mask = 0;
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if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
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(1u << si_get_shaderbuf_slot(0)))
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saved_writable_mask |= 1 << 0;
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/* Set the DCC buffer. */
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assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX);
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assert(tex->buffer.bo_size <= UINT_MAX);
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@ -744,7 +683,6 @@ void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uin
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sb.buffer = &tex->buffer.b.b;
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sb.buffer_offset = tex->surface.meta_offset;
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sb.buffer_size = tex->buffer.bo_size - sb.buffer_offset;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &sb, 0x1);
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sctx->cs_user_data[0] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) |
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(tex->surface.u.gfx9.color.dcc_height << 16);
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@ -776,16 +714,7 @@ void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uin
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info.grid[1] = DIV_ROUND_UP(height, info.block[1]);
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info.grid[2] = depth;
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si_launch_grid_internal(sctx, &info, *shader, flags);
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enum si_cache_policy cache_policy = get_cache_policy(sctx, coher, tex->surface.meta_size);
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if (flags & SI_OP_SYNC_AFTER)
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sctx->flags |= cache_policy == L2_BYPASS ? SI_CONTEXT_WB_L2 : 0;
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/* Restore states. */
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, &saved_sb, saved_writable_mask);
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pipe_resource_reference(&saved_sb.buffer, NULL);
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si_launch_grid_internal_ssbos(sctx, &info, *shader, flags, coher, 1, &sb, 0x1);
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}
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/* Expand FMASK to make it identity, so that image stores can ignore it. */
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@ -1402,6 +1402,10 @@ unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
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enum si_cache_policy cache_policy);
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void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *info,
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void *shader, unsigned flags);
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void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
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void *shader, unsigned flags, enum si_coherency coher,
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unsigned num_buffers, const struct pipe_shader_buffer *buffers,
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unsigned writeable_bitmask);
|
||||
enum si_clear_method {
|
||||
SI_CP_DMA_CLEAR_METHOD,
|
||||
SI_COMPUTE_CLEAR_METHOD,
|
||||
|
|
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|||
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|
@ -1500,8 +1500,6 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_q
|
|||
|
||||
ssbo[2] = ssbo[1];
|
||||
|
||||
sctx->b.bind_compute_state(&sctx->b, sctx->query_result_shader);
|
||||
|
||||
grid.block[0] = 1;
|
||||
grid.block[1] = 1;
|
||||
grid.block[2] = 1;
|
||||
|
|
@ -1566,8 +1564,6 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_q
|
|||
si_resource(resource)->TC_L2_dirty = true;
|
||||
}
|
||||
|
||||
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo, 1 << 2);
|
||||
|
||||
if (wait && qbuf == &query->buffer) {
|
||||
uint64_t va;
|
||||
|
||||
|
|
@ -1580,9 +1576,9 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_q
|
|||
|
||||
si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x80000000, 0x80000000, WAIT_REG_MEM_EQUAL);
|
||||
}
|
||||
|
||||
sctx->b.launch_grid(&sctx->b, &grid);
|
||||
sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PFP_SYNC_ME;
|
||||
si_launch_grid_internal_ssbos(sctx, &grid, sctx->query_result_shader,
|
||||
SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
|
||||
3, ssbo, 0x4);
|
||||
}
|
||||
|
||||
si_restore_qbo_state(sctx, &saved_state);
|
||||
|
|
|
|||
|
|
@ -292,10 +292,7 @@ int si_get_perfcounter_group_info(struct si_screen *, unsigned index,
|
|||
struct pipe_driver_query_group_info *info);
|
||||
|
||||
struct si_qbo_state {
|
||||
void *saved_compute;
|
||||
struct pipe_constant_buffer saved_const0;
|
||||
struct pipe_shader_buffer saved_ssbo[3];
|
||||
unsigned saved_ssbo_writable_mask;
|
||||
};
|
||||
|
||||
#endif /* SI_QUERY_H */
|
||||
|
|
|
|||
|
|
@ -1333,30 +1333,12 @@ void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enab
|
|||
|
||||
void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
|
||||
{
|
||||
st->saved_compute = sctx->cs_shader_state.program;
|
||||
|
||||
si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
|
||||
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
|
||||
|
||||
st->saved_ssbo_writable_mask = 0;
|
||||
|
||||
for (unsigned i = 0; i < 3; i++) {
|
||||
if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
|
||||
(1u << si_get_shaderbuf_slot(i)))
|
||||
st->saved_ssbo_writable_mask |= 1 << i;
|
||||
}
|
||||
}
|
||||
|
||||
void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
|
||||
{
|
||||
sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
|
||||
|
||||
sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
|
||||
|
||||
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
|
||||
st->saved_ssbo_writable_mask);
|
||||
for (unsigned i = 0; i < 3; ++i)
|
||||
pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
|
||||
}
|
||||
|
||||
static void si_emit_db_render_state(struct si_context *sctx)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue