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i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().

Browse source 
Cuts 1.5k of .text.

Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2015-11-02 12:12:44 -08:00
parent 9b978046eb
commit f9a9ba5eac
12 changed files with 195 additions and 239 deletions
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5
src/mesa/drivers/dri/i965/brw_ir_vec4.h
View file

@ -41,11 +41,6 @@ public:
src_reg(enum brw_reg_file file, int nr, const glsl_type *type);
src_reg();
src_reg(float f);
src_reg(uint32_t u);
src_reg(int32_t i);
src_reg(uint8_t vf[4]);
src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
src_reg(struct brw_reg reg);
bool equals(const src_reg &r) const;

67
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -71,51 +71,6 @@ src_reg::src_reg()
init();
}
src_reg::src_reg(float f)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->f = f;
}
src_reg::src_reg(uint32_t u)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->ud = u;
}
src_reg::src_reg(int32_t i)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->d = i;
}
src_reg::src_reg(uint8_t vf[4])
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->ud, vf, sizeof(unsigned));
}
src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
{
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->ud = (vf0 << 0) | (vf1 << 8) | (vf2 << 16) | (vf3 << 24);
}
src_reg::src_reg(struct brw_reg reg) :
backend_reg(reg)
{
@ -382,7 +337,9 @@ vec4_visitor::opt_vector_float()
remaining_channels &= ~inst->dst.writemask;
if (remaining_channels == 0) {
vec4_instruction *mov = MOV(inst->dst, imm);
unsigned vf;
memcpy(&vf, imm, sizeof(vf));
vec4_instruction *mov = MOV(inst->dst, brw_imm_vf(vf));
mov->dst.type = BRW_REGISTER_TYPE_F;
mov->dst.writemask = WRITEMASK_XYZW;
inst->insert_after(block, mov);
@ -657,13 +614,13 @@ vec4_visitor::opt_algebraic()
inst->opcode = BRW_OPCODE_MOV;
switch (inst->src[0].type) {
case BRW_REGISTER_TYPE_F:
inst->src[0] = src_reg(0.0f);
inst->src[0] = brw_imm_f(0.0f);
break;
case BRW_REGISTER_TYPE_D:
inst->src[0] = src_reg(0);
inst->src[0] = brw_imm_d(0);
break;
case BRW_REGISTER_TYPE_UD:
inst->src[0] = src_reg(0u);
inst->src[0] = brw_imm_ud(0u);
break;
default:
unreachable("not reached");
@ -1232,7 +1189,7 @@ vec4_visitor::eliminate_find_live_channel()
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
if (depth == 0) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = src_reg(0);
inst->src[0] = brw_imm_d(0);
inst->force_writemask_all = true;
progress = true;
}
@ -1701,7 +1658,7 @@ vec4_visitor::emit_shader_time_end()
*/
src_reg reset_end = shader_end_time;
reset_end.swizzle = BRW_SWIZZLE_ZZZZ;
vec4_instruction *test = emit(AND(dst_null_d(), reset_end, src_reg(1u)));
vec4_instruction *test = emit(AND(dst_null_ud(), reset_end, brw_imm_ud(1u)));
test->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
@ -1715,12 +1672,12 @@ vec4_visitor::emit_shader_time_end()
* is 2 cycles. Remove that overhead, so I can forget about that when
* trying to determine the time taken for single instructions.
*/
emit(ADD(diff, src_reg(diff), src_reg(-2u)));
emit(ADD(diff, src_reg(diff), brw_imm_ud(-2u)));
emit_shader_time_write(0, src_reg(diff));
emit_shader_time_write(1, src_reg(1u));
emit_shader_time_write(1, brw_imm_ud(1u));
emit(BRW_OPCODE_ELSE);
emit_shader_time_write(2, src_reg(1u));
emit_shader_time_write(2, brw_imm_ud(1u));
emit(BRW_OPCODE_ENDIF);
}
@ -1736,7 +1693,7 @@ vec4_visitor::emit_shader_time_write(int shader_time_subindex, src_reg value)
offset.type = BRW_REGISTER_TYPE_UD;
int index = shader_time_index * 3 + shader_time_subindex;
emit(MOV(offset, src_reg(index * SHADER_TIME_STRIDE)));
emit(MOV(offset, brw_imm_d(index * SHADER_TIME_STRIDE)));
time.type = BRW_REGISTER_TYPE_UD;
emit(MOV(time, value));

2
src/mesa/drivers/dri/i965/brw_vec4_builder.h
View file

@ -484,7 +484,7 @@ namespace brw {
const dst_reg x_times_one_minus_a = vgrf(dst.type);
MUL(y_times_a, y, a);
ADD(one_minus_a, negate(a), src_reg(1.0f));
ADD(one_minus_a, negate(a), brw_imm_f(1.0f));
MUL(x_times_one_minus_a, x, src_reg(one_minus_a));
return ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a));
}

38
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
View file

@ -153,7 +153,7 @@ vec4_gs_visitor::emit_prolog()
*/
this->current_annotation = "clear r0.2";
dst_reg r0(retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, 0u);
vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u));
inst->force_writemask_all = true;
/* Create a virtual register to hold the vertex count */
@ -161,7 +161,7 @@ vec4_gs_visitor::emit_prolog()
/* Initialize the vertex_count register to 0 */
this->current_annotation = "initialize vertex_count";
inst = emit(MOV(dst_reg(this->vertex_count), 0u));
inst = emit(MOV(dst_reg(this->vertex_count), brw_imm_ud(0u)));
inst->force_writemask_all = true;
if (c->control_data_header_size_bits > 0) {
@ -176,7 +176,7 @@ vec4_gs_visitor::emit_prolog()
*/
if (c->control_data_header_size_bits <= 32) {
this->current_annotation = "initialize control data bits";
inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
inst->force_writemask_all = true;
}
}
@ -274,7 +274,7 @@ vec4_gs_visitor::emit_urb_write_header(int mrf)
vec4_instruction *inst = emit(MOV(mrf_reg, r0));
inst->force_writemask_all = true;
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, this->vertex_count,
(uint32_t) gs_prog_data->output_vertex_size_hwords);
brw_imm_ud(gs_prog_data->output_vertex_size_hwords));
}
@ -354,11 +354,12 @@ vec4_gs_visitor::emit_control_data_bits()
src_reg dword_index(this, glsl_type::uint_type);
if (urb_write_flags) {
src_reg prev_count(this, glsl_type::uint_type);
emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
emit(ADD(dst_reg(prev_count), this->vertex_count,
brw_imm_ud(0xffffffffu)));
unsigned log2_bits_per_vertex =
_mesa_fls(c->control_data_bits_per_vertex);
emit(SHR(dst_reg(dword_index), prev_count,
(uint32_t) (6 - log2_bits_per_vertex)));
brw_imm_ud(6 - log2_bits_per_vertex)));
}
/* Start building the URB write message. The first MRF gets a copy of
@ -375,8 +376,9 @@ vec4_gs_visitor::emit_control_data_bits()
* the appropriate OWORD within the control data header.
*/
src_reg per_slot_offset(this, glsl_type::uint_type);
emit(SHR(dst_reg(per_slot_offset), dword_index, 2u));
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset, 1u);
emit(SHR(dst_reg(per_slot_offset), dword_index, brw_imm_ud(2u)));
emit(GS_OPCODE_SET_WRITE_OFFSET, mrf_reg, per_slot_offset,
brw_imm_ud(1u));
}
if (urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS) {
@ -388,10 +390,10 @@ vec4_gs_visitor::emit_control_data_bits()
* together.
*/
src_reg channel(this, glsl_type::uint_type);
inst = emit(AND(dst_reg(channel), dword_index, 3u));
inst = emit(AND(dst_reg(channel), dword_index, brw_imm_ud(3u)));
inst->force_writemask_all = true;
src_reg one(this, glsl_type::uint_type);
inst = emit(MOV(dst_reg(one), 1u));
inst = emit(MOV(dst_reg(one), brw_imm_ud(1u)));
inst->force_writemask_all = true;
src_reg channel_mask(this, glsl_type::uint_type);
inst = emit(SHL(dst_reg(channel_mask), one, channel));
@ -441,11 +443,11 @@ vec4_gs_visitor::set_stream_control_data_bits(unsigned stream_id)
/* reg::sid = stream_id */
src_reg sid(this, glsl_type::uint_type);
emit(MOV(dst_reg(sid), stream_id));
emit(MOV(dst_reg(sid), brw_imm_ud(stream_id)));
/* reg:shift_count = 2 * (vertex_count - 1) */
src_reg shift_count(this, glsl_type::uint_type);
emit(SHL(dst_reg(shift_count), this->vertex_count, 1u));
emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u)));
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this
@ -503,8 +505,8 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
* vertex_count & (32 / bits_per_vertex - 1) == 0
*/
vec4_instruction *inst =
emit(AND(dst_null_d(), this->vertex_count,
(uint32_t) (32 / c->control_data_bits_per_vertex - 1)));
emit(AND(dst_null_ud(), this->vertex_count,
brw_imm_ud(32 / c->control_data_bits_per_vertex - 1)));
inst->conditional_mod = BRW_CONDITIONAL_Z;
emit(IF(BRW_PREDICATE_NORMAL));
@ -512,7 +514,7 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
/* If vertex_count is 0, then no control data bits have been
* accumulated yet, so we skip emitting them.
*/
emit(CMP(dst_null_d(), this->vertex_count, 0u,
emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u),
BRW_CONDITIONAL_NEQ));
emit(IF(BRW_PREDICATE_NORMAL));
emit_control_data_bits();
@ -525,7 +527,7 @@ vec4_gs_visitor::gs_emit_vertex(int stream_id)
* effect of any call to EndPrimitive() that the shader may have
* made before outputting its first vertex.
*/
inst = emit(MOV(dst_reg(this->control_data_bits), 0u));
inst = emit(MOV(dst_reg(this->control_data_bits), brw_imm_ud(0u)));
inst->force_writemask_all = true;
}
emit(BRW_OPCODE_ENDIF);
@ -586,9 +588,9 @@ vec4_gs_visitor::gs_end_primitive()
/* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
src_reg one(this, glsl_type::uint_type);
emit(MOV(dst_reg(one), 1u));
emit(MOV(dst_reg(one), brw_imm_ud(1u)));
src_reg prev_count(this, glsl_type::uint_type);
emit(ADD(dst_reg(prev_count), this->vertex_count, 0xffffffffu));
emit(ADD(dst_reg(prev_count), this->vertex_count, brw_imm_ud(0xffffffffu)));
src_reg mask(this, glsl_type::uint_type);
/* Note: we're relying on the fact that the GEN SHL instruction only pays
* attention to the lower 5 bits of its second source argument, so on this

78
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
View file

@ -373,7 +373,7 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
}
reg.writemask = writemask;
emit(MOV(reg, src_reg(instr->value.i[i])));
emit(MOV(reg, brw_imm_d(instr->value.i[i])));
remaining &= ~writemask;
}
@ -444,10 +444,10 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
inst->base_mrf = 2;
inst->mlen = 1; /* always at least one */
inst->src[1] = src_reg(index);
inst->src[1] = brw_imm_ud(index);
/* MRF for the first parameter */
src_reg lod = src_reg(0);
src_reg lod = brw_imm_d(0);
int param_base = inst->base_mrf;
int writemask = WRITEMASK_X;
emit(MOV(dst_reg(MRF, param_base, glsl_type::int_type, writemask), lod));
@ -471,12 +471,12 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
if (const_uniform_block) {
unsigned index = prog_data->base.binding_table.ssbo_start +
const_uniform_block->u[0];
surf_index = src_reg(index);
surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index);
} else {
surf_index = src_reg(this, glsl_type::uint_type);
emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[1], 1),
src_reg(prog_data->base.binding_table.ssbo_start)));
brw_imm_ud(prog_data->base.binding_table.ssbo_start)));
surf_index = emit_uniformize(surf_index);
brw_mark_surface_used(&prog_data->base,
@ -491,7 +491,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
emit(MOV(dst_reg(offset_reg), get_nir_src(instr->src[2], 1)));
} else {
const_offset_bytes = instr->const_index[0];
emit(MOV(dst_reg(offset_reg), src_reg(const_offset_bytes)));
emit(MOV(dst_reg(offset_reg), brw_imm_ud(const_offset_bytes)));
}
/* Value */
@ -566,7 +566,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
if (skipped_channels > 0) {
if (!has_indirect) {
const_offset_bytes += 4 * skipped_channels;
offset_reg = src_reg(const_offset_bytes);
offset_reg = brw_imm_ud(const_offset_bytes);
} else {
emit(ADD(dst_reg(offset_reg), offset_reg,
brw_imm_ud(4 * skipped_channels)));
@ -614,13 +614,13 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
if (const_uniform_block) {
unsigned index = prog_data->base.binding_table.ssbo_start +
const_uniform_block->u[0];
surf_index = src_reg(index);
surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index);
} else {
surf_index = src_reg(this, glsl_type::uint_type);
emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0], 1),
src_reg(prog_data->base.binding_table.ssbo_start)));
brw_imm_ud(prog_data->base.binding_table.ssbo_start)));
surf_index = emit_uniformize(surf_index);
/* Assume this may touch any UBO. It would be nice to provide
@ -637,7 +637,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
emit(MOV(dst_reg(offset_reg), get_nir_src(instr->src[1], 1)));
} else {
const_offset_bytes = instr->const_index[0];
emit(MOV(dst_reg(offset_reg), src_reg(const_offset_bytes)));
emit(MOV(dst_reg(offset_reg), brw_imm_ud((const_offset_bytes))));
}
/* Read the vector */
@ -762,7 +762,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
*/
const unsigned index = prog_data->base.binding_table.ubo_start +
const_block_index->u[0];
surf_index = src_reg(index);
surf_index = brw_imm_ud(index);
brw_mark_surface_used(&prog_data->base, index);
} else {
/* The block index is not a constant. Evaluate the index expression
@ -772,7 +772,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
surf_index = src_reg(this, glsl_type::uint_type);
emit(ADD(dst_reg(surf_index), get_nir_src(instr->src[0], nir_type_int,
instr->num_components),
src_reg(prog_data->base.binding_table.ubo_start)));
brw_imm_ud(prog_data->base.binding_table.ubo_start)));
surf_index = emit_uniformize(surf_index);
/* Assume this may touch any UBO. It would be nice to provide
@ -787,11 +787,11 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
src_reg offset;
if (!has_indirect) {
offset = src_reg(const_offset / 16);
offset = brw_imm_ud(const_offset / 16);
} else {
offset = src_reg(this, glsl_type::uint_type);
emit(SHR(dst_reg(offset), get_nir_src(instr->src[1], nir_type_int, 1),
src_reg(4u)));
brw_imm_ud(4u)));
}
src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
@ -848,12 +848,12 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr)
if (const_surface) {
unsigned surf_index = prog_data->base.binding_table.ssbo_start +
const_surface->u[0];
surface = src_reg(surf_index);
surface = brw_imm_ud(surf_index);
brw_mark_surface_used(&prog_data->base, surf_index);
} else {
surface = src_reg(this, glsl_type::uint_type);
emit(ADD(dst_reg(surface), get_nir_src(instr->src[0]),
src_reg(prog_data->base.binding_table.ssbo_start)));
brw_imm_ud(prog_data->base.binding_table.ssbo_start)));
/* Assume this may touch any UBO. This is the same we do for other
* UBO/SSBO accesses with non-constant surface.
@ -1174,8 +1174,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz),
brw_conditional_for_nir_comparison(instr->op)));
emit(MOV(dst, src_reg(0)));
inst = emit(MOV(dst, src_reg(~0)));
emit(MOV(dst, brw_imm_d(0)));
inst = emit(MOV(dst, brw_imm_d(~0)));
inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
break;
}
@ -1192,8 +1192,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
emit(CMP(dst_null_d(), swizzle(op[0], swiz), swizzle(op[1], swiz),
brw_conditional_for_nir_comparison(instr->op)));
emit(MOV(dst, src_reg(0)));
inst = emit(MOV(dst, src_reg(~0)));
emit(MOV(dst, brw_imm_d(0)));
inst = emit(MOV(dst, brw_imm_d(~0)));
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
}
@ -1235,11 +1235,11 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
break;
case nir_op_f2b:
emit(CMP(dst, op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
break;
case nir_op_i2b:
emit(CMP(dst, op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ));
break;
case nir_op_fnoise1_1:
@ -1321,9 +1321,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
* subtract the result from 31 to convert the MSB count into an LSB count.
*/
src_reg src(dst);
emit(CMP(dst_null_d(), src, src_reg(-1), BRW_CONDITIONAL_NZ));
emit(CMP(dst_null_d(), src, brw_imm_d(-1), BRW_CONDITIONAL_NZ));
inst = emit(ADD(dst, src, src_reg(31)));
inst = emit(ADD(dst, src, brw_imm_d(31)));
inst->predicate = BRW_PREDICATE_NORMAL;
inst->src[0].negate = true;
break;
@ -1364,13 +1364,13 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
* zero.
*/
emit(CMP(dst_null_f(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
emit(CMP(dst_null_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
op[0].type = BRW_REGISTER_TYPE_UD;
dst.type = BRW_REGISTER_TYPE_UD;
emit(AND(dst, op[0], src_reg(0x80000000u)));
emit(AND(dst, op[0], brw_imm_ud(0x80000000u)));
inst = emit(OR(dst, src_reg(dst), src_reg(0x3f800000u)));
inst = emit(OR(dst, src_reg(dst), brw_imm_ud(0x3f800000u)));
inst->predicate = BRW_PREDICATE_NORMAL;
dst.type = BRW_REGISTER_TYPE_F;
@ -1385,9 +1385,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
* -> non-negative val generates 0x00000000.
* Predicated OR sets 1 if val is positive.
*/
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_G));
emit(ASR(dst, op[0], src_reg(31)));
inst = emit(OR(dst, src_reg(dst), src_reg(1)));
emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G));
emit(ASR(dst, op[0], brw_imm_d(31)));
inst = emit(OR(dst, src_reg(dst), brw_imm_d(1)));
inst->predicate = BRW_PREDICATE_NORMAL;
break;
@ -1418,7 +1418,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
break;
case nir_op_bcsel:
emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ));
inst = emit(BRW_OPCODE_SEL, dst, op[1], op[2]);
switch (dst.writemask) {
case WRITEMASK_X:
@ -1465,10 +1465,10 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
unsigned swiz =
brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
emit(CMP(dst_null_d(), swizzle(op[0], swiz), src_reg(0),
emit(CMP(dst_null_d(), swizzle(op[0], swiz), brw_imm_d(0),
BRW_CONDITIONAL_NZ));
emit(MOV(dst, src_reg(0)));
inst = emit(MOV(dst, src_reg(~0)));
emit(MOV(dst, brw_imm_d(0)));
inst = emit(MOV(dst, brw_imm_d(~0)));
inst->predicate = BRW_PREDICATE_ALIGN16_ANY4H;
break;
}
@ -1502,7 +1502,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
dst_reg masked = dst_reg(this, glsl_type::int_type);
masked.writemask = dst.writemask;
emit(AND(masked, src_reg(dst), src_reg(1)));
emit(AND(masked, src_reg(dst), brw_imm_d(1)));
src_reg masked_neg = src_reg(masked);
masked_neg.negate = true;
emit(MOV(retype(dst, BRW_REGISTER_TYPE_D), masked_neg));
@ -1575,7 +1575,7 @@ void
vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
{
unsigned sampler = instr->sampler_index;
src_reg sampler_reg = src_reg(sampler);
src_reg sampler_reg = brw_imm_ud(sampler);
src_reg coordinate;
const glsl_type *coord_type = NULL;
src_reg shadow_comparitor;
@ -1595,7 +1595,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
if (instr->op == nir_texop_tg4) {
int swiz = GET_SWZ(key_tex->swizzles[sampler], instr->component);
if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
emit(MOV(dest, src_reg(swiz == SWIZZLE_ONE ? 1.0f : 0.0f)));
emit(MOV(dest, brw_imm_f(swiz == SWIZZLE_ONE ? 1.0f : 0.0f)));
return;
}
}
@ -1658,7 +1658,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coord_type, coordinate, sampler_reg);
} else {
mcs = src_reg(0u);
mcs = brw_imm_ud(0u);
}
mcs = retype(mcs, BRW_REGISTER_TYPE_UD);
break;
@ -1686,7 +1686,7 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
/* Emit code to evaluate the actual indexing expression */
src_reg src = get_nir_src(instr->src[i].src, 1);
src_reg temp(this, glsl_type::uint_type);
emit(ADD(dst_reg(temp), src, src_reg(sampler)));
emit(ADD(dst_reg(temp), src, brw_imm_ud(sampler)));
sampler_reg = emit_uniformize(temp);
break;
}

8
src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
View file

@ -71,7 +71,7 @@ namespace {
bld.MOV(writemask(tmp, mask), src);
if (n < 4)
bld.MOV(writemask(tmp, ~mask), 0);
bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1);
}
@ -143,7 +143,7 @@ namespace brw {
/* Emit the message send instruction. */
const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
vec4_instruction *inst =
bld.emit(op, dst, src_reg(payload), usurface, arg);
bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
inst->mlen = sz;
inst->regs_written = ret_sz;
inst->header_size = header_sz;
@ -235,7 +235,7 @@ namespace brw {
const vec4_builder ubld = bld.exec_all();
const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.MOV(dst, src_reg(0));
ubld.MOV(dst, brw_imm_d(0));
if (bld.shader->devinfo->gen == 7 &&
!bld.shader->devinfo->is_haswell) {
@ -243,7 +243,7 @@ namespace brw {
* have no SIMD4x2 variant. We only use the two X channels
* in that case, mask everything else out.
*/
ubld.MOV(writemask(dst, WRITEMASK_W), src_reg(0x11));
ubld.MOV(writemask(dst, WRITEMASK_W), brw_imm_d(0x11));
}
return src_reg(dst);

94
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -408,7 +408,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
* You should inspect the disasm output in order to verify that the MOV is
* not optimized away.
*/
emit(MOV(tmp_dst, src_reg(0x12345678u)));
emit(MOV(tmp_dst, brw_imm_ud(0x12345678u)));
#endif
/* Give tmp the form below, where "." means untouched.
@ -427,7 +427,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
* 0xhhhh0000
*/
tmp_src.swizzle = BRW_SWIZZLE_YYYY;
emit(SHL(dst, tmp_src, src_reg(16u)));
emit(SHL(dst, tmp_src, brw_imm_ud(16u)));
/* Finally, give the write-channels of dst the form of packHalf2x16's
* output:
@ -466,10 +466,10 @@ vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
src_reg tmp_src(tmp_dst);
tmp_dst.writemask = WRITEMASK_X;
emit(AND(tmp_dst, src0, src_reg(0xffffu)));
emit(AND(tmp_dst, src0, brw_imm_ud(0xffffu)));
tmp_dst.writemask = WRITEMASK_Y;
emit(SHR(tmp_dst, src0, src_reg(16u)));
emit(SHR(tmp_dst, src0, brw_imm_ud(16u)));
dst.writemask = WRITEMASK_XY;
emit(F16TO32(dst, tmp_src));
@ -484,7 +484,7 @@ vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0)
* vector float and a type-converting MOV.
*/
dst_reg shift(this, glsl_type::uvec4_type);
emit(MOV(shift, src_reg(0x00, 0x60, 0x70, 0x78)));
emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
dst_reg shifted(this, glsl_type::uvec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
@ -494,7 +494,7 @@ vec4_visitor::emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0)
dst_reg f(this, glsl_type::vec4_type);
emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
emit(MUL(dst, src_reg(f), src_reg(1.0f / 255.0f)));
emit(MUL(dst, src_reg(f), brw_imm_f(1.0f / 255.0f)));
}
void
@ -506,7 +506,7 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0)
* vector float and a type-converting MOV.
*/
dst_reg shift(this, glsl_type::uvec4_type);
emit(MOV(shift, src_reg(0x00, 0x60, 0x70, 0x78)));
emit(MOV(shift, brw_imm_vf4(0x00, 0x60, 0x70, 0x78)));
dst_reg shifted(this, glsl_type::uvec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
@ -517,11 +517,11 @@ vec4_visitor::emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0)
emit(VEC4_OPCODE_MOV_BYTES, f, src_reg(shifted));
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(f), src_reg(1.0f / 127.0f)));
emit(MUL(scaled, src_reg(f), brw_imm_f(1.0f / 127.0f)));
dst_reg max(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), src_reg(1.0f));
emit_minmax(BRW_CONDITIONAL_GE, max, src_reg(scaled), brw_imm_f(-1.0f));
emit_minmax(BRW_CONDITIONAL_L, dst, src_reg(max), brw_imm_f(1.0f));
}
void
@ -532,7 +532,7 @@ vec4_visitor::emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0)
inst->saturate = true;
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(saturated), src_reg(255.0f)));
emit(MUL(scaled, src_reg(saturated), brw_imm_f(255.0f)));
dst_reg rounded(this, glsl_type::vec4_type);
emit(RNDE(rounded, src_reg(scaled)));
@ -548,13 +548,13 @@ void
vec4_visitor::emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0)
{
dst_reg max(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_GE, max, src0, src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_GE, max, src0, brw_imm_f(-1.0f));
dst_reg min(this, glsl_type::vec4_type);
emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), src_reg(1.0f));
emit_minmax(BRW_CONDITIONAL_L, min, src_reg(max), brw_imm_f(1.0f));
dst_reg scaled(this, glsl_type::vec4_type);
emit(MUL(scaled, src_reg(min), src_reg(127.0f)));
emit(MUL(scaled, src_reg(min), brw_imm_f(127.0f)));
dst_reg rounded(this, glsl_type::vec4_type);
emit(RNDE(rounded, src_reg(scaled)));
@ -715,7 +715,7 @@ vec4_visitor::emit_lrp(const dst_reg &dst,
x_times_one_minus_a.writemask = dst.writemask;
emit(MUL(y_times_a, y, a));
emit(ADD(one_minus_a, negate(a), src_reg(1.0f)));
emit(ADD(one_minus_a, negate(a), brw_imm_f(1.0f)));
emit(MUL(x_times_one_minus_a, x, src_reg(one_minus_a)));
return emit(ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a)));
}
@ -849,7 +849,7 @@ vec4_visitor::emit_mcs_fetch(const glsl_type *coordinate_type,
coordinate));
emit(MOV(dst_reg(MRF, param_base, coordinate_type, zero_mask),
src_reg(0)));
brw_imm_d(0)));
emit(inst);
return src_reg(inst->dst);
@ -889,7 +889,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
*/
if (op == ir_tex || op == ir_query_levels) {
assert(lod.file == BAD_FILE);
lod = src_reg(0.0f);
lod = brw_imm_f(0.0f);
}
enum opcode opcode;
@ -959,7 +959,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
if (zero_mask != 0) {
emit(MOV(dst_reg(MRF, param_base, coordinate.type, zero_mask),
src_reg(0)));
brw_imm_d(0)));
}
/* Load the shadow comparitor */
if (shadow_comparitor.file != BAD_FILE && op != ir_txd && (op != ir_tg4 || offset_value.file == BAD_FILE)) {
@ -1058,7 +1058,7 @@ vec4_visitor::emit_texture(ir_texture_opcode op,
if (op == ir_txs && is_cube_array) {
emit_math(SHADER_OPCODE_INT_QUOTIENT,
writemask(inst->dst, WRITEMASK_Z),
src_reg(inst->dst), src_reg(6));
src_reg(inst->dst), brw_imm_d(6));
}
if (devinfo->gen == 6 && op == ir_tg4) {
@ -1083,7 +1083,7 @@ vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
dst_f.type = BRW_REGISTER_TYPE_F;
/* Convert from UNORM to UINT */
emit(MUL(dst_f, src_reg(dst_f), src_reg((float)((1 << width) - 1))));
emit(MUL(dst_f, src_reg(dst_f), brw_imm_f((float)((1 << width) - 1))));
emit(MOV(dst, src_reg(dst_f)));
if (wa & WA_SIGN) {
@ -1091,8 +1091,8 @@ vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
* shifting the sign bit into place, then shifting back
* preserving sign.
*/
emit(SHL(dst, src_reg(dst), src_reg(32 - width)));
emit(ASR(dst, src_reg(dst), src_reg(32 - width)));
emit(SHL(dst, src_reg(dst), brw_imm_d(32 - width)));
emit(ASR(dst, src_reg(dst), brw_imm_d(32 - width)));
}
}
@ -1168,12 +1168,12 @@ vec4_visitor::swizzle_result(ir_texture_opcode op, dst_reg dest,
if (zero_mask) {
swizzled_result.writemask = zero_mask;
emit(MOV(swizzled_result, src_reg(0.0f)));
emit(MOV(swizzled_result, brw_imm_f(0.0f)));
}
if (one_mask) {
swizzled_result.writemask = one_mask;
emit(MOV(swizzled_result, src_reg(1.0f)));
emit(MOV(swizzled_result, brw_imm_f(1.0f)));
}
}
@ -1220,7 +1220,7 @@ vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
*/
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
src_payload,
src_reg(surf_index), src_reg(atomic_op));
brw_imm_ud(surf_index), brw_imm_ud(atomic_op));
inst->mlen = mlen;
}
@ -1240,7 +1240,7 @@ vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
*/
vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst,
src_reg(offset),
src_reg(surf_index), src_reg(1));
brw_imm_ud(surf_index), brw_imm_d(1));
inst->mlen = 1;
}
@ -1281,14 +1281,14 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
dst_reg header1_w = header1;
header1_w.writemask = WRITEMASK_W;
emit(MOV(header1, 0u));
emit(MOV(header1, brw_imm_ud(0u)));
if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
src_reg psiz = src_reg(output_reg[VARYING_SLOT_PSIZ]);
current_annotation = "Point size";
emit(MUL(header1_w, psiz, src_reg((float)(1 << 11))));
emit(AND(header1_w, src_reg(header1_w), 0x7ff << 8));
emit(MUL(header1_w, psiz, brw_imm_f((float)(1 << 11))));
emit(AND(header1_w, src_reg(header1_w), brw_imm_d(0x7ff << 8)));
}
if (output_reg[VARYING_SLOT_CLIP_DIST0].file != BAD_FILE) {
@ -1296,13 +1296,13 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
dst_reg flags0 = dst_reg(this, glsl_type::uint_type);
dst_reg flags1 = dst_reg(this, glsl_type::uint_type);
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0]), src_reg(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, src_reg(0));
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST0]), brw_imm_f(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags0, brw_imm_d(0));
emit(OR(header1_w, src_reg(header1_w), src_reg(flags0)));
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1]), src_reg(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, src_reg(0));
emit(SHL(flags1, src_reg(flags1), src_reg(4)));
emit(CMP(dst_null_f(), src_reg(output_reg[VARYING_SLOT_CLIP_DIST1]), brw_imm_f(0.0f), BRW_CONDITIONAL_L));
emit(VS_OPCODE_UNPACK_FLAGS_SIMD4X2, flags1, brw_imm_d(0));
emit(SHL(flags1, src_reg(flags1), brw_imm_d(4)));
emit(OR(header1_w, src_reg(header1_w), src_reg(flags1)));
}
@ -1319,20 +1319,20 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
output_reg[BRW_VARYING_SLOT_NDC].file != BAD_FILE) {
src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]);
ndc_w.swizzle = BRW_SWIZZLE_WWWW;
emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
emit(CMP(dst_null_f(), ndc_w, brw_imm_f(0.0f), BRW_CONDITIONAL_L));
vec4_instruction *inst;
inst = emit(OR(header1_w, src_reg(header1_w), src_reg(1u << 6)));
inst = emit(OR(header1_w, src_reg(header1_w), brw_imm_ud(1u << 6)));
inst->predicate = BRW_PREDICATE_NORMAL;
output_reg[BRW_VARYING_SLOT_NDC].type = BRW_REGISTER_TYPE_F;
inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC], src_reg(0.0f)));
inst = emit(MOV(output_reg[BRW_VARYING_SLOT_NDC], brw_imm_f(0.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
}
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
} else if (devinfo->gen < 6) {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)));
} else {
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), brw_imm_d(0)));
if (prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) {
dst_reg reg_w = reg;
reg_w.writemask = WRITEMASK_W;
@ -1524,13 +1524,13 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst,
src_reg index = src_reg(this, glsl_type::int_type);
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
brw_imm_d(reg_offset)));
emit_before(block, inst, MUL(dst_reg(index), index,
src_reg(message_header_scale)));
brw_imm_d(message_header_scale)));
return index;
} else {
return src_reg(reg_offset * message_header_scale);
return brw_imm_d(reg_offset * message_header_scale);
}
}
@ -1542,24 +1542,24 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
src_reg index = src_reg(this, glsl_type::int_type);
emit_before(block, inst, ADD(dst_reg(index), *reladdr,
src_reg(reg_offset)));
brw_imm_d(reg_offset)));
/* Pre-gen6, the message header uses byte offsets instead of vec4
* (16-byte) offset units.
*/
if (devinfo->gen < 6) {
emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
emit_before(block, inst, MUL(dst_reg(index), index, brw_imm_d(16)));
}
return index;
} else if (devinfo->gen >= 8) {
/* Store the offset in a GRF so we can send-from-GRF. */
src_reg offset = src_reg(this, glsl_type::int_type);
emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
emit_before(block, inst, MOV(dst_reg(offset), brw_imm_d(reg_offset)));
return offset;
} else {
int message_header_scale = devinfo->gen < 6 ? 16 : 1;
return src_reg(reg_offset * message_header_scale);
return brw_imm_d(reg_offset * message_header_scale);
}
}
@ -1748,7 +1748,7 @@ vec4_visitor::emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
reg_offset);
emit_pull_constant_load_reg(temp,
src_reg(index),
brw_imm_ud(index),
offset,
block, inst);

20
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp
View file

@ -50,7 +50,7 @@ vec4_vs_visitor::emit_prolog()
dst_reg dst = reg;
dst.type = brw_type_for_base_type(glsl_type::vec4_type);
dst.writemask = (1 << (wa_flags & BRW_ATTRIB_WA_COMPONENT_MASK)) - 1;
emit(MUL(dst, src_reg(dst), src_reg(1.0f / 65536.0f)));
emit(MUL(dst, src_reg(dst), brw_imm_f(1.0f / 65536.0f)));
}
/* Do sign recovery for 2101010 formats if required. */
@ -58,8 +58,8 @@ vec4_vs_visitor::emit_prolog()
if (sign_recovery_shift.file == BAD_FILE) {
/* shift constant: <22,22,22,30> */
sign_recovery_shift = dst_reg(this, glsl_type::uvec4_type);
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_XYZ), src_reg(22u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_W), src_reg(30u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_XYZ), brw_imm_ud(22u)));
emit(MOV(writemask(sign_recovery_shift, WRITEMASK_W), brw_imm_ud(30u)));
}
emit(SHL(reg_ud, src_reg(reg_ud), src_reg(sign_recovery_shift)));
@ -87,16 +87,16 @@ vec4_vs_visitor::emit_prolog()
/* mul constant: 1 / (2^(b-1) - 1) */
es3_normalize_factor = dst_reg(this, glsl_type::vec4_type);
emit(MOV(writemask(es3_normalize_factor, WRITEMASK_XYZ),
src_reg(1.0f / ((1<<9) - 1))));
brw_imm_f(1.0f / ((1<<9) - 1))));
emit(MOV(writemask(es3_normalize_factor, WRITEMASK_W),
src_reg(1.0f / ((1<<1) - 1))));
brw_imm_f(1.0f / ((1<<1) - 1))));
}
dst_reg dst = reg;
dst.type = brw_type_for_base_type(glsl_type::vec4_type);
emit(MOV(dst, src_reg(reg_d)));
emit(MUL(dst, src_reg(dst), src_reg(es3_normalize_factor)));
emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst), src_reg(-1.0f));
emit_minmax(BRW_CONDITIONAL_GE, dst, src_reg(dst), brw_imm_f(-1.0f));
} else {
/* The following equations are from the OpenGL 3.2 specification:
*
@ -113,9 +113,9 @@ vec4_vs_visitor::emit_prolog()
/* 1 / (2^b - 1) for b=<10,10,10,2> */
normalize_factor = dst_reg(this, glsl_type::vec4_type);
emit(MOV(writemask(normalize_factor, WRITEMASK_XYZ),
src_reg(1.0f / ((1<<10) - 1))));
brw_imm_f(1.0f / ((1<<10) - 1))));
emit(MOV(writemask(normalize_factor, WRITEMASK_W),
src_reg(1.0f / ((1<<2) - 1))));
brw_imm_f(1.0f / ((1<<2) - 1))));
}
dst_reg dst = reg;
@ -124,8 +124,8 @@ vec4_vs_visitor::emit_prolog()
/* For signed normalization, we want the numerator to be 2c+1. */
if (wa_flags & BRW_ATTRIB_WA_SIGN) {
emit(MUL(dst, src_reg(dst), src_reg(2.0f)));
emit(ADD(dst, src_reg(dst), src_reg(1.0f)));
emit(MUL(dst, src_reg(dst), brw_imm_f(2.0f)));
emit(ADD(dst, src_reg(dst), brw_imm_f(1.0f)));
}
emit(MUL(dst, src_reg(dst), src_reg(normalize_factor)));

78
src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp
View file

@ -65,7 +65,7 @@ gen6_gs_visitor::emit_prolog()
(prog_data->vue_map.num_slots + 1) *
nir->info.gs.vertices_out);
this->vertex_output_offset = src_reg(this, glsl_type::uint_type);
emit(MOV(dst_reg(this->vertex_output_offset), src_reg(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
/* MRF 1 will be the header for all messages (FF_SYNC and URB_WRITES),
* so initialize it once to R0.
@ -87,13 +87,13 @@ gen6_gs_visitor::emit_prolog()
* headers.
*/
this->first_vertex = src_reg(this, glsl_type::uint_type);
emit(MOV(dst_reg(this->first_vertex), URB_WRITE_PRIM_START));
emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(URB_WRITE_PRIM_START)));
/* The FF_SYNC message requires to know the number of primitives generated,
* so keep a counter for this.
*/
this->prim_count = src_reg(this, glsl_type::uint_type);
emit(MOV(dst_reg(this->prim_count), 0u));
emit(MOV(dst_reg(this->prim_count), brw_imm_ud(0u)));
if (gs_prog_data->gen6_xfb_enabled) {
/* Create a virtual register to hold destination indices in SOL */
@ -170,7 +170,7 @@ gen6_gs_visitor::gs_emit_vertex(int stream_id)
}
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, 1u));
this->vertex_output_offset, brw_imm_ud(1u)));
}
/* Now buffer flags for this vertex */
@ -181,9 +181,9 @@ gen6_gs_visitor::gs_emit_vertex(int stream_id)
/* If we are outputting points, then every vertex has PrimStart and
* PrimEnd set.
*/
emit(MOV(dst, (_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) |
URB_WRITE_PRIM_START | URB_WRITE_PRIM_END));
emit(ADD(dst_reg(this->prim_count), this->prim_count, 1u));
emit(MOV(dst, brw_imm_d((_3DPRIM_POINTLIST << URB_WRITE_PRIM_TYPE_SHIFT) |
URB_WRITE_PRIM_START | URB_WRITE_PRIM_END)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u)));
} else {
/* Otherwise, we can only set the PrimStart flag, which we have stored
* in the first_vertex register. We will have to wait until we execute
@ -191,11 +191,12 @@ gen6_gs_visitor::gs_emit_vertex(int stream_id)
* vertex.
*/
emit(OR(dst, this->first_vertex,
(gs_prog_data->output_topology << URB_WRITE_PRIM_TYPE_SHIFT)));
emit(MOV(dst_reg(this->first_vertex), 0u));
brw_imm_ud(gs_prog_data->output_topology <<
URB_WRITE_PRIM_TYPE_SHIFT)));
emit(MOV(dst_reg(this->first_vertex), brw_imm_ud(0u)));
}
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, 1u));
this->vertex_output_offset, brw_imm_ud(1u)));
}
void
@ -218,10 +219,10 @@ gen6_gs_visitor::gs_end_primitive()
* below).
*/
unsigned num_output_vertices = nir->info.gs.vertices_out;
emit(CMP(dst_null_d(), this->vertex_count, src_reg(num_output_vertices + 1),
BRW_CONDITIONAL_L));
vec4_instruction *inst = emit(CMP(dst_null_d(),
this->vertex_count, 0u,
emit(CMP(dst_null_ud(), this->vertex_count,
brw_imm_ud(num_output_vertices + 1), BRW_CONDITIONAL_L));
vec4_instruction *inst = emit(CMP(dst_null_ud(),
this->vertex_count, brw_imm_ud(0u),
BRW_CONDITIONAL_NEQ));
inst->predicate = BRW_PREDICATE_NORMAL;
emit(IF(BRW_PREDICATE_NORMAL));
@ -231,19 +232,19 @@ gen6_gs_visitor::gs_end_primitive()
* vertex.
*/
src_reg offset(this, glsl_type::uint_type);
emit(ADD(dst_reg(offset), this->vertex_output_offset, src_reg(-1)));
emit(ADD(dst_reg(offset), this->vertex_output_offset, brw_imm_d(-1)));
src_reg dst(this->vertex_output);
dst.reladdr = ralloc(mem_ctx, src_reg);
memcpy(dst.reladdr, &offset, sizeof(src_reg));
emit(OR(dst_reg(dst), dst, URB_WRITE_PRIM_END));
emit(ADD(dst_reg(this->prim_count), this->prim_count, 1u));
emit(OR(dst_reg(dst), dst, brw_imm_d(URB_WRITE_PRIM_END)));
emit(ADD(dst_reg(this->prim_count), this->prim_count, brw_imm_ud(1u)));
/* Set the first vertex flag to indicate that the next vertex will start
* a primitive.
*/
emit(MOV(dst_reg(this->first_vertex), URB_WRITE_PRIM_START));
emit(MOV(dst_reg(this->first_vertex), brw_imm_d(URB_WRITE_PRIM_START)));
}
emit(BRW_OPCODE_ENDIF);
}
@ -262,7 +263,8 @@ gen6_gs_visitor::emit_urb_write_header(int mrf)
*/
src_reg flags_offset(this, glsl_type::uint_type);
emit(ADD(dst_reg(flags_offset),
this->vertex_output_offset, src_reg(prog_data->vue_map.num_slots)));
this->vertex_output_offset,
brw_imm_d(prog_data->vue_map.num_slots)));
src_reg flags_data(this->vertex_output);
flags_data.reladdr = ralloc(mem_ctx, src_reg);
@ -321,7 +323,7 @@ gen6_gs_visitor::emit_thread_end()
* points because in the point case we set PrimEnd on all vertices.
*/
if (nir->info.gs.output_primitive != GL_POINTS) {
emit(CMP(dst_null_d(), this->first_vertex, 0u, BRW_CONDITIONAL_Z));
emit(CMP(dst_null_ud(), this->first_vertex, brw_imm_ud(0u), BRW_CONDITIONAL_Z));
emit(IF(BRW_PREDICATE_NORMAL));
gs_end_primitive();
emit(BRW_OPCODE_ENDIF);
@ -347,7 +349,7 @@ gen6_gs_visitor::emit_thread_end()
int max_usable_mrf = FIRST_SPILL_MRF(devinfo->gen);
/* Issue the FF_SYNC message and obtain the initial VUE handle. */
emit(CMP(dst_null_d(), this->vertex_count, 0u, BRW_CONDITIONAL_G));
emit(CMP(dst_null_ud(), this->vertex_count, brw_imm_ud(0u), BRW_CONDITIONAL_G));
emit(IF(BRW_PREDICATE_NORMAL));
{
this->current_annotation = "gen6 thread end: ff_sync";
@ -364,15 +366,15 @@ gen6_gs_visitor::emit_thread_end()
dst_reg(this->temp), this->prim_count, this->svbi);
} else {
inst = emit(GS_OPCODE_FF_SYNC,
dst_reg(this->temp), this->prim_count, src_reg(0u));
dst_reg(this->temp), this->prim_count, brw_imm_ud(0u));
}
inst->base_mrf = base_mrf;
/* Loop over all buffered vertices and emit URB write messages */
this->current_annotation = "gen6 thread end: urb writes init";
src_reg vertex(this, glsl_type::uint_type);
emit(MOV(dst_reg(vertex), 0u));
emit(MOV(dst_reg(this->vertex_output_offset), 0u));
emit(MOV(dst_reg(vertex), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
this->current_annotation = "gen6 thread end: urb writes";
emit(BRW_OPCODE_DO);
@ -416,7 +418,7 @@ gen6_gs_visitor::emit_thread_end()
mrf++;
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, 1u));
this->vertex_output_offset, brw_imm_ud(1u)));
/* If this was max_usable_mrf, we can't fit anything more into
* this URB WRITE. Same if we reached the max. message length.
@ -437,9 +439,9 @@ gen6_gs_visitor::emit_thread_end()
* writing the next vertex.
*/
emit(ADD(dst_reg(this->vertex_output_offset),
this->vertex_output_offset, 1u));
this->vertex_output_offset, brw_imm_ud(1u)));
emit(ADD(dst_reg(vertex), vertex, 1u));
emit(ADD(dst_reg(vertex), vertex, brw_imm_ud(1u)));
}
emit(BRW_OPCODE_WHILE);
@ -468,8 +470,8 @@ gen6_gs_visitor::emit_thread_end()
if (gs_prog_data->gen6_xfb_enabled) {
/* When emitting EOT, set SONumPrimsWritten Increment Value. */
src_reg data(this, glsl_type::uint_type);
emit(AND(dst_reg(data), this->sol_prim_written, src_reg(0xffffu)));
emit(SHL(dst_reg(data), data, src_reg(16u)));
emit(AND(dst_reg(data), this->sol_prim_written, brw_imm_ud(0xffffu)));
emit(SHL(dst_reg(data), data, brw_imm_ud(16u)));
emit(GS_OPCODE_SET_DWORD_2, dst_reg(MRF, base_mrf), data);
}
@ -588,8 +590,8 @@ gen6_gs_visitor::xfb_write()
this->current_annotation = "gen6 thread end: svb writes init";
emit(MOV(dst_reg(this->vertex_output_offset), 0u));
emit(MOV(dst_reg(this->sol_prim_written), 0u));
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_ud(0u)));
emit(MOV(dst_reg(this->sol_prim_written), brw_imm_ud(0u)));
/* Check that at least one primitive can be written
*
@ -600,7 +602,7 @@ gen6_gs_visitor::xfb_write()
* transform feedback is in interleaved or separate attribs mode.
*/
src_reg sol_temp(this, glsl_type::uvec4_type);
emit(ADD(dst_reg(sol_temp), this->svbi, src_reg(num_verts)));
emit(ADD(dst_reg(sol_temp), this->svbi, brw_imm_ud(num_verts)));
/* Compare SVBI calculated number with the maximum value, which is
* in R1.4 (previously saved in this->max_svbi) for gen6.
@ -623,7 +625,7 @@ gen6_gs_visitor::xfb_write()
/* Write transform feedback data for all processed vertices. */
for (int i = 0; i < (int)nir->info.gs.vertices_out; i++) {
emit(MOV(dst_reg(sol_temp), i));
emit(MOV(dst_reg(sol_temp), brw_imm_d(i)));
emit(CMP(dst_null_d(), sol_temp, this->vertex_count,
BRW_CONDITIONAL_L));
emit(IF(BRW_PREDICATE_NORMAL));
@ -644,8 +646,8 @@ gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
/* Check for buffer overflow: we need room to write the complete primitive
* (all vertices). Otherwise, avoid writing any vertices for it
*/
emit(ADD(dst_reg(sol_temp), this->sol_prim_written, 1u));
emit(MUL(dst_reg(sol_temp), sol_temp, src_reg(num_verts)));
emit(ADD(dst_reg(sol_temp), this->sol_prim_written, brw_imm_ud(1u)));
emit(MUL(dst_reg(sol_temp), sol_temp, brw_imm_ud(num_verts)));
emit(ADD(dst_reg(sol_temp), sol_temp, this->svbi));
emit(CMP(dst_null_d(), sol_temp, this->max_svbi, BRW_CONDITIONAL_LE));
emit(IF(BRW_PREDICATE_NORMAL));
@ -683,7 +685,7 @@ gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
src_reg data(this->vertex_output);
data.reladdr = ralloc(mem_ctx, src_reg);
int offset = get_vertex_output_offset_for_varying(vertex, varying);
emit(MOV(dst_reg(this->vertex_output_offset), offset));
emit(MOV(dst_reg(this->vertex_output_offset), brw_imm_d(offset)));
memcpy(data.reladdr, &this->vertex_output_offset, sizeof(src_reg));
data.type = output_reg[varying].type;
@ -710,9 +712,9 @@ gen6_gs_visitor::xfb_program(unsigned vertex, unsigned num_verts)
*/
emit(ADD(dst_reg(this->destination_indices),
this->destination_indices,
src_reg(num_verts)));
brw_imm_ud(num_verts)));
emit(ADD(dst_reg(this->sol_prim_written),
this->sol_prim_written, 1u));
this->sol_prim_written, brw_imm_ud(1u)));
}
}

38
src/mesa/drivers/dri/i965/test_vec4_cmod_propagation.cpp
View file

@ -145,7 +145,7 @@ TEST_F(cmod_propagation_test, basic)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
@ -181,7 +181,7 @@ TEST_F(cmod_propagation_test, basic_different_dst_writemask)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.ADD(dest, src0, src1);
@ -217,8 +217,8 @@ TEST_F(cmod_propagation_test, andz_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg one(1);
src_reg zero(brw_imm_f(0.0f));
src_reg one(brw_imm_d(1));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_Z,
@ -253,7 +253,7 @@ TEST_F(cmod_propagation_test, non_cmod_instruction)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::uint_type);
src_reg src0 = src_reg(v, glsl_type::uint_type);
src_reg zero(0u);
src_reg zero(brw_imm_ud(0u));
bld.FBL(dest, src0);
bld.CMP(bld.null_reg_ud(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
@ -288,7 +288,7 @@ TEST_F(cmod_propagation_test, intervening_flag_write)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_GE);
@ -328,7 +328,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest0, src0, src1);
set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero));
bld.CMP(bld.null_reg_f(), src_reg(dest0), zero, BRW_CONDITIONAL_GE);
@ -367,7 +367,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::vec2_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(offset(dest, 2), src0, src1);
bld.emit(SHADER_OPCODE_TEX, dest, src2)
->regs_written = 4;
@ -409,7 +409,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg src2 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
dest_null.writemask = WRITEMASK_X;
@ -449,7 +449,7 @@ TEST_F(cmod_propagation_test, negate)
dst_reg dest = dst_reg(v, glsl_type::float_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg src1 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
src_reg tmp_src = src_reg(dest);
tmp_src.negate = true;
@ -521,7 +521,7 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::int_type);
src_reg src1 = src_reg(v, glsl_type::int_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.ADD(dest, src0, src1);
bld.CMP(bld.null_reg_f(), retype(src_reg(dest), BRW_REGISTER_TYPE_F), zero,
BRW_CONDITIONAL_GE);
@ -555,8 +555,8 @@ TEST_F(cmod_propagation_test, andnz_non_one)
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
src_reg src0 = src_reg(v, glsl_type::float_type);
src_reg zero(0.0f);
src_reg nonone(38);
src_reg zero(brw_imm_f(0.0f));
src_reg nonone(brw_imm_d(38));
bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L);
set_condmod(BRW_CONDITIONAL_NZ,
@ -594,7 +594,7 @@ TEST_F(cmod_propagation_test, basic_vec4)
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
bld.MUL(dest, src0, src1);
bld.CMP(bld.null_reg_f(), src_reg(dest), zero, BRW_CONDITIONAL_NZ);
@ -628,7 +628,7 @@ TEST_F(cmod_propagation_test, basic_vec4_different_dst_writemask)
dest.writemask = WRITEMASK_X;
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
dst_reg dest_null = bld.null_reg_f();
bld.MUL(dest, src0, src1);
@ -668,7 +668,7 @@ TEST_F(cmod_propagation_test, mad_one_component_vec4)
src_reg src2 = src_reg(v, glsl_type::vec4_type);
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
@ -710,7 +710,7 @@ TEST_F(cmod_propagation_test, mad_more_one_component_vec4)
src_reg src2 = src_reg(v, glsl_type::vec4_type);
src0.swizzle = src1.swizzle = src2.swizzle = BRW_SWIZZLE_XXXX;
src2.negate = true;
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg tmp(dest);
tmp.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_f();
@ -751,7 +751,7 @@ TEST_F(cmod_propagation_test, cmp_mov_vec4)
src_reg src0 = src_reg(v, glsl_type::ivec4_type);
src0.swizzle = BRW_SWIZZLE_XXXX;
src0.file = UNIFORM;
src_reg nonone = retype(src_reg(16), BRW_REGISTER_TYPE_D);
src_reg nonone = retype(brw_imm_d(16), BRW_REGISTER_TYPE_D);
src_reg mov_src = src_reg(dest);
mov_src.swizzle = BRW_SWIZZLE_XXXX;
dst_reg dest_null = bld.null_reg_d();
@ -790,7 +790,7 @@ TEST_F(cmod_propagation_test, mul_cmp_different_channels_vec4)
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
src_reg src0 = src_reg(v, glsl_type::vec4_type);
src_reg src1 = src_reg(v, glsl_type::vec4_type);
src_reg zero(0.0f);
src_reg zero(brw_imm_f(0.0f));
src_reg cmp_src = src_reg(dest);
cmp_src.swizzle = BRW_SWIZZLE4(0,1,3,2);

2
src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp
View file

@ -162,7 +162,7 @@ TEST_F(copy_propagation_test, test_swizzle_writemask)
SWIZZLE_X,
SWIZZLE_Z))));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), src_reg(1.0f)));
v->emit(v->MOV(writemask(a, WRITEMASK_XYZ), brw_imm_f(1.0f)));
vec4_instruction *test_mov =
v->MOV(c, swizzle(src_reg(b), BRW_SWIZZLE4(SWIZZLE_W,

4
src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp
View file

@ -135,7 +135,7 @@ TEST_F(register_coalesce_test, test_compute_to_mrf)
m0.writemask = WRITEMASK_X;
m0.type = BRW_REGISTER_TYPE_F;
vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
v->emit(v->MOV(m0, src_reg(temp)));
register_coalesce(v);
@ -159,7 +159,7 @@ TEST_F(register_coalesce_test, test_multiple_use)
m1.type = BRW_REGISTER_TYPE_F;
src_reg src = src_reg(temp);
vec4_instruction *mul = v->emit(v->MUL(temp, something, src_reg(1.0f)));
vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
src.swizzle = BRW_SWIZZLE_XXXX;
v->emit(v->MOV(m0, src));
src.swizzle = BRW_SWIZZLE_XYZW;