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pan/midgard: Express allocated registers as offsets
Rather than supplying a mask/swizzle to compose with the original, just supply the offset of the allocated register so we can directly offset the mask/swizzle, without resorting to composition. This is simpler, cleaner, and will generalize to non-32-bit. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
parent
c1d36eb115
commit
f98e9a2771
1 changed files with 63 additions and 105 deletions
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@ -61,64 +61,38 @@ static unsigned reg_type_to_mask[WORK_STRIDE] = {
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0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
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};
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static unsigned reg_type_to_swizzle[WORK_STRIDE] = {
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SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_Y, COMPONENT_Z, COMPONENT_W, COMPONENT_W),
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SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_Y, COMPONENT_Z, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_Z, COMPONENT_W, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_Y, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_Z, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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SWIZZLE(COMPONENT_W, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
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};
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struct phys_reg {
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/* Physical register: 0-31 */
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unsigned reg;
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unsigned mask;
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unsigned swizzle;
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/* Byte offset into the physical register: 0-15 */
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unsigned offset;
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/* Number of bytes in a component of this register */
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unsigned size;
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};
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/* Given the mask/swizzle of both the register and the original source,
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* compose to find the actual mask/swizzle to give the hardware */
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/* Shift each component up by reg_offset and shift all components horizontally
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* by dst_offset. TODO: Generalize to !32-bit */
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static unsigned
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compose_writemask(unsigned mask, struct phys_reg reg)
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offset_swizzle(unsigned swizzle, unsigned reg_offset, unsigned srcsize, unsigned dst_offset, unsigned dstsize)
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{
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/* Note: the reg mask is guaranteed to be contiguous. So we shift
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* into the X place, compose via a simple AND, and shift back */
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unsigned out = 0;
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unsigned shift = __builtin_ctz(reg.mask);
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return ((reg.mask >> shift) & mask) << shift;
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}
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signed reg_comp = reg_offset / srcsize;
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signed dst_comp = dst_offset / dstsize;
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static unsigned
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compose_swizzle(unsigned swizzle, unsigned mask,
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struct phys_reg reg, struct phys_reg dst)
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{
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unsigned out = pan_compose_swizzle(swizzle, reg.swizzle);
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assert(reg_comp * srcsize == reg_offset);
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assert(dst_comp * dstsize == dst_offset);
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/* Based on the register mask, we need to adjust over. E.g if we're
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* writing to yz, a base swizzle of xy__ becomes _xy_. Save the
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* original first component (x). But to prevent duplicate shifting
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* (only applies to ALU -- mask param is set to xyzw out on L/S to
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* prevent changes), we have to account for the shift inherent to the
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* original writemask */
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for (signed c = 0; c < 4; ++c) {
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signed comp = MAX2(c - dst_comp, 0);
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signed s = (swizzle >> (2*comp)) & 0x3;
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out |= (MIN2(s + reg_comp, 3) << (2*c));
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}
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unsigned rep = out & 0x3;
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unsigned shift = __builtin_ctz(dst.mask) - __builtin_ctz(mask);
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unsigned shifted = out << (2*shift);
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/* ..but we fill in the gaps so it appears to replicate */
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for (unsigned s = 0; s < shift; ++s)
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shifted |= rep << (2*s);
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return shifted;
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return out;
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}
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/* Helper to return the default phys_reg for a given register */
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@ -128,8 +102,8 @@ default_phys_reg(int reg)
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{
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struct phys_reg r = {
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.reg = reg,
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.mask = 0xF, /* xyzw */
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.swizzle = 0xE4 /* xyzw */
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.offset = 0,
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.size = 4
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};
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return r;
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@ -139,7 +113,7 @@ default_phys_reg(int reg)
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* register corresponds to */
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static struct phys_reg
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index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg)
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index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg, midgard_reg_mode size)
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{
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/* Check for special cases */
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if (reg == ~0)
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@ -163,10 +137,12 @@ index_to_reg(compiler_context *ctx, struct ra_graph *g, unsigned reg)
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else if (phys == SHADOW_R0)
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phys = 0;
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unsigned bytes = mir_bytes_for_mode(size);
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struct phys_reg r = {
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.reg = phys,
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.mask = reg_type_to_mask[type],
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.swizzle = reg_type_to_swizzle[type]
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.offset = __builtin_ctz(reg_type_to_mask[type]) * bytes,
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.size = bytes
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};
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/* Report that we actually use this register, and return it */
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@ -702,20 +678,19 @@ install_registers_instr(
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if (ins->compact_branch)
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return;
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struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0]);
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struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1]);
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest);
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struct phys_reg src1 = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
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struct phys_reg src2 = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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unsigned uncomposed_mask = ins->mask;
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ins->mask = compose_writemask(uncomposed_mask, dest);
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mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
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/* Adjust the dest mask if necessary. Mostly this is a no-op
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* but it matters for dot products */
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dest.mask = effective_writemask(&ins->alu, ins->mask);
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unsigned dest_offset =
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GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? 0 :
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dest.offset;
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midgard_vector_alu_src mod1 =
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vector_alu_from_unsigned(ins->alu.src1);
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mod1.swizzle = compose_swizzle(mod1.swizzle, uncomposed_mask, src1, dest);
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mod1.swizzle = offset_swizzle(mod1.swizzle, src1.offset, src1.size, dest_offset, dest.size);
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ins->alu.src1 = vector_alu_srco_unsigned(mod1);
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ins->registers.src1_reg = src1.reg;
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@ -736,8 +711,7 @@ install_registers_instr(
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} else {
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midgard_vector_alu_src mod2 =
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vector_alu_from_unsigned(ins->alu.src2);
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mod2.swizzle = compose_swizzle(
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mod2.swizzle, uncomposed_mask, src2, dest);
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mod2.swizzle = offset_swizzle(mod2.swizzle, src2.offset, src2.size, dest_offset, dest.size);
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ins->alu.src2 = vector_alu_srco_unsigned(mod2);
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ins->registers.src2_reg = src2.reg;
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@ -755,54 +729,38 @@ install_registers_instr(
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bool encodes_src = OP_IS_STORE(ins->load_store.op);
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if (encodes_src) {
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struct phys_reg src = index_to_reg(ctx, g, ins->src[0]);
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struct phys_reg src = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
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assert(src.reg == 26 || src.reg == 27);
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ins->load_store.reg = src.reg - 26;
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unsigned shift = __builtin_ctz(src.mask);
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unsigned adjusted_mask = src.mask >> shift;
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assert(((adjusted_mask + 1) & adjusted_mask) == 0);
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unsigned new_swizzle = 0;
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for (unsigned q = 0; q < 4; ++q) {
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unsigned c = (ins->load_store.swizzle >> (2*q)) & 3;
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new_swizzle |= (c + shift) << (2*q);
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}
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ins->load_store.swizzle = compose_swizzle(
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new_swizzle, src.mask,
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default_phys_reg(0), src);
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ins->load_store.swizzle = offset_swizzle(ins->load_store.swizzle, src.offset, src.size, 0, 4);
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} else {
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struct phys_reg src = index_to_reg(ctx, g, ins->dest);
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struct phys_reg dst = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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ins->load_store.reg = src.reg;
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ins->load_store.swizzle = compose_swizzle(
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ins->load_store.swizzle, 0xF,
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default_phys_reg(0), src);
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ins->mask = compose_writemask(
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ins->mask, src);
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ins->load_store.reg = dst.reg;
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ins->load_store.swizzle = offset_swizzle(ins->load_store.swizzle, 0, 4, dst.offset, dst.size);
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mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
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}
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/* We also follow up by actual arguments */
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int src2 =
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encodes_src ? ins->src[1] : ins->src[0];
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unsigned src2_idx = encodes_src ? 1 : 0;
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unsigned src3_idx = encodes_src ? 2 : 1;
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int src3 =
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encodes_src ? ins->src[2] : ins->src[1];
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unsigned src2 = ins->src[src2_idx];
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unsigned src3 = ins->src[src3_idx];
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if (src2 >= 0) {
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struct phys_reg src = index_to_reg(ctx, g, src2);
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unsigned component = __builtin_ctz(src.mask);
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if (src2 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src2, mir_srcsize(ins, src2_idx));
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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ins->load_store.arg_1 |= midgard_ldst_reg(src.reg, component);
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}
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if (src3 >= 0) {
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struct phys_reg src = index_to_reg(ctx, g, src3);
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unsigned component = __builtin_ctz(src.mask);
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if (src3 != ~0) {
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struct phys_reg src = index_to_reg(ctx, g, src3, mir_srcsize(ins, src3_idx));
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unsigned component = src.offset / src.size;
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assert(component * src.size == src.offset);
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ins->load_store.arg_2 |= midgard_ldst_reg(src.reg, component);
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}
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@ -811,9 +769,9 @@ install_registers_instr(
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case TAG_TEXTURE_4: {
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/* Grab RA results */
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest);
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struct phys_reg coord = index_to_reg(ctx, g, ins->src[0]);
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struct phys_reg lod = index_to_reg(ctx, g, ins->src[1]);
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struct phys_reg dest = index_to_reg(ctx, g, ins->dest, mir_typesize(ins));
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struct phys_reg coord = index_to_reg(ctx, g, ins->src[0], mir_srcsize(ins, 0));
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struct phys_reg lod = index_to_reg(ctx, g, ins->src[1], mir_srcsize(ins, 1));
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assert(dest.reg == 28 || dest.reg == 29);
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assert(coord.reg == 28 || coord.reg == 29);
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@ -823,23 +781,23 @@ install_registers_instr(
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ins->texture.in_reg_upper = 0;
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ins->texture.in_reg_select = coord.reg - 28;
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ins->texture.in_reg_swizzle =
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pan_compose_swizzle(ins->texture.in_reg_swizzle, coord.swizzle);
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offset_swizzle(ins->texture.in_reg_swizzle, coord.offset, coord.size, 0, 4);
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/* Next, install the destination */
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ins->texture.out_full = 1;
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ins->texture.out_upper = 0;
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ins->texture.out_reg_select = dest.reg - 28;
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ins->texture.swizzle =
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compose_swizzle(ins->texture.swizzle, dest.mask, dest, dest);
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ins->mask =
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compose_writemask(ins->mask, dest);
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offset_swizzle(ins->texture.swizzle, 0, 4, dest.offset, coord.size);
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mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
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/* If there is a register LOD/bias, use it */
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if (ins->src[1] != ~0) {
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assert(!(lod.offset & 3));
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midgard_tex_register_select sel = {
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.select = lod.reg,
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.full = 1,
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.component = lod.swizzle & 3,
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.component = lod.offset / 4
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};
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uint8_t packed;
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