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radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER

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Caches are always flushed at IB boundary.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
This commit is contained in:
Marek Olšák 2016-10-01 00:46:39 +02:00
parent ca1d1e0e19
commit f92113c5a1
1 changed files with 3 additions and 4 deletions
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7
src/gallium/drivers/radeonsi/si_state.c
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@ -3414,14 +3414,13 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
if (flags & PIPE_BARRIER_FRAMEBUFFER)
sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
PIPE_BARRIER_FRAMEBUFFER |
if (flags & (PIPE_BARRIER_FRAMEBUFFER |
PIPE_BARRIER_INDIRECT_BUFFER)) {
/* Not sure if INV_GLOBAL_L2 is the best thing here.
*
* We need to make sure that TC L1 & L2 are written back to
* memory, because neither CPU accesses nor CB fetches consider
* TC, but there's no need to invalidate any TC cache lines. */
* memory, because CB fetches don't consider TC, but there's
* no need to invalidate any TC cache lines. */
sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
}
}