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https://gitlab.freedesktop.org/mesa/mesa.git
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Nouveau: copy nv30_vertprog.c to nv20.
Signed-off-by: Pekka Paalanen <pq@iki.fi>
This commit is contained in:
Pekka Paalanen
parent
0344b0e32e
commit
f910371b37
1 changed files with 838 additions and 0 deletions
838
src/gallium/drivers/nv20/nv30_vertprog.c
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838
src/gallium/drivers/nv20/nv30_vertprog.c
Normal file
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@ -0,0 +1,838 @@
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#include "pipe/p_context.h"
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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#include "pipe/p_shader_tokens.h"
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#include "tgsi/tgsi_parse.h"
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#include "tgsi/tgsi_dump.h"
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#include "nv30_context.h"
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#include "nv30_state.h"
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/* TODO (at least...):
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* 1. Indexed consts + ARL
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* 2. Arb. swz/negation
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* 3. NV_vp11, NV_vp2, NV_vp3 features
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* - extra arith opcodes
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* - branching
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* - texture sampling
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* - indexed attribs
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* - indexed results
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* 4. bugs
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*/
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#define SWZ_X 0
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#define SWZ_Y 1
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#define SWZ_Z 2
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#define SWZ_W 3
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#define MASK_X 8
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#define MASK_Y 4
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#define MASK_Z 2
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#define MASK_W 1
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#define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W)
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#define DEF_SCALE 0
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#define DEF_CTEST 0
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#include "nv30_shader.h"
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#define swz(s,x,y,z,w) nv30_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w)
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#define neg(s) nv30_sr_neg((s))
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#define abs(s) nv30_sr_abs((s))
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struct nv30_vpc {
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struct nv30_vertex_program *vp;
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struct nv30_vertex_program_exec *vpi;
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unsigned output_map[PIPE_MAX_SHADER_OUTPUTS];
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int high_temp;
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int temp_temp_count;
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struct nv30_sreg *imm;
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unsigned nr_imm;
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};
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static struct nv30_sreg
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temp(struct nv30_vpc *vpc)
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{
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int idx;
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idx = vpc->temp_temp_count++;
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idx += vpc->high_temp + 1;
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return nv30_sr(NV30SR_TEMP, idx);
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}
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static struct nv30_sreg
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constant(struct nv30_vpc *vpc, int pipe, float x, float y, float z, float w)
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{
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struct nv30_vertex_program *vp = vpc->vp;
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struct nv30_vertex_program_data *vpd;
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int idx;
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if (pipe >= 0) {
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for (idx = 0; idx < vp->nr_consts; idx++) {
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if (vp->consts[idx].index == pipe)
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return nv30_sr(NV30SR_CONST, idx);
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}
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}
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idx = vp->nr_consts++;
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vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
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vpd = &vp->consts[idx];
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vpd->index = pipe;
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vpd->value[0] = x;
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vpd->value[1] = y;
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vpd->value[2] = z;
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vpd->value[3] = w;
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return nv30_sr(NV30SR_CONST, idx);
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}
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#define arith(cc,s,o,d,m,s0,s1,s2) \
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nv30_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2))
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static void
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emit_src(struct nv30_vpc *vpc, uint32_t *hw, int pos, struct nv30_sreg src)
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{
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struct nv30_vertex_program *vp = vpc->vp;
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uint32_t sr = 0;
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switch (src.type) {
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case NV30SR_TEMP:
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sr |= (NV30_VP_SRC_REG_TYPE_TEMP << NV30_VP_SRC_REG_TYPE_SHIFT);
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sr |= (src.index << NV30_VP_SRC_TEMP_SRC_SHIFT);
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break;
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case NV30SR_INPUT:
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sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
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NV30_VP_SRC_REG_TYPE_SHIFT);
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vp->ir |= (1 << src.index);
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hw[1] |= (src.index << NV30_VP_INST_INPUT_SRC_SHIFT);
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break;
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case NV30SR_CONST:
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sr |= (NV30_VP_SRC_REG_TYPE_CONST <<
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NV30_VP_SRC_REG_TYPE_SHIFT);
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assert(vpc->vpi->const_index == -1 ||
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vpc->vpi->const_index == src.index);
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vpc->vpi->const_index = src.index;
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break;
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case NV30SR_NONE:
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sr |= (NV30_VP_SRC_REG_TYPE_INPUT <<
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NV30_VP_SRC_REG_TYPE_SHIFT);
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break;
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default:
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assert(0);
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}
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if (src.negate)
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sr |= NV30_VP_SRC_NEGATE;
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if (src.abs)
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hw[0] |= (1 << (21 + pos));
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sr |= ((src.swz[0] << NV30_VP_SRC_SWZ_X_SHIFT) |
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(src.swz[1] << NV30_VP_SRC_SWZ_Y_SHIFT) |
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(src.swz[2] << NV30_VP_SRC_SWZ_Z_SHIFT) |
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(src.swz[3] << NV30_VP_SRC_SWZ_W_SHIFT));
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/*
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* |VVV|
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* d<EFBFBD>.<EFBFBD>b
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* \u/
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*
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*/
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switch (pos) {
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case 0:
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hw[1] |= ((sr & NV30_VP_SRC0_HIGH_MASK) >>
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NV30_VP_SRC0_HIGH_SHIFT) << NV30_VP_INST_SRC0H_SHIFT;
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hw[2] |= (sr & NV30_VP_SRC0_LOW_MASK) <<
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NV30_VP_INST_SRC0L_SHIFT;
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break;
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case 1:
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hw[2] |= sr << NV30_VP_INST_SRC1_SHIFT;
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break;
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case 2:
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hw[2] |= ((sr & NV30_VP_SRC2_HIGH_MASK) >>
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NV30_VP_SRC2_HIGH_SHIFT) << NV30_VP_INST_SRC2H_SHIFT;
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hw[3] |= (sr & NV30_VP_SRC2_LOW_MASK) <<
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NV30_VP_INST_SRC2L_SHIFT;
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break;
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default:
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assert(0);
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}
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}
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static void
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emit_dst(struct nv30_vpc *vpc, uint32_t *hw, int slot, struct nv30_sreg dst)
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{
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struct nv30_vertex_program *vp = vpc->vp;
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switch (dst.type) {
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case NV30SR_TEMP:
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hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
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break;
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case NV30SR_OUTPUT:
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switch (dst.index) {
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case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
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case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
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case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
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case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
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case NV30_VP_INST_DEST_FOGC : vp->or |= (1 << 4); break;
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case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
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case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
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case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
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case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
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case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
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case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
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case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
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case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
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case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
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default:
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break;
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}
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hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
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hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
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/*XXX: no way this is entirely correct, someone needs to
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* figure out what exactly it is.
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*/
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hw[3] |= 0x800;
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break;
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default:
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assert(0);
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}
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}
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static void
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nv30_vp_arith(struct nv30_vpc *vpc, int slot, int op,
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struct nv30_sreg dst, int mask,
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struct nv30_sreg s0, struct nv30_sreg s1,
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struct nv30_sreg s2)
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{
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struct nv30_vertex_program *vp = vpc->vp;
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uint32_t *hw;
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vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
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vpc->vpi = &vp->insns[vp->nr_insns - 1];
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memset(vpc->vpi, 0, sizeof(*vpc->vpi));
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vpc->vpi->const_index = -1;
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hw = vpc->vpi->data;
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hw[0] |= (NV30_VP_INST_COND_TR << NV30_VP_INST_COND_SHIFT);
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hw[0] |= ((0 << NV30_VP_INST_COND_SWZ_X_SHIFT) |
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(1 << NV30_VP_INST_COND_SWZ_Y_SHIFT) |
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(2 << NV30_VP_INST_COND_SWZ_Z_SHIFT) |
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(3 << NV30_VP_INST_COND_SWZ_W_SHIFT));
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hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
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// hw[3] |= NV30_VP_INST_SCA_DEST_TEMP_MASK;
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// hw[3] |= (mask << NV30_VP_INST_VEC_WRITEMASK_SHIFT);
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if (dst.type == NV30SR_OUTPUT) {
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if (slot)
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hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
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else
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hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
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} else {
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if (slot)
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hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
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else
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hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
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}
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emit_dst(vpc, hw, slot, dst);
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emit_src(vpc, hw, 0, s0);
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emit_src(vpc, hw, 1, s1);
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emit_src(vpc, hw, 2, s2);
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}
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static INLINE struct nv30_sreg
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tgsi_src(struct nv30_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
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struct nv30_sreg src;
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switch (fsrc->SrcRegister.File) {
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case TGSI_FILE_INPUT:
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src = nv30_sr(NV30SR_INPUT, fsrc->SrcRegister.Index);
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break;
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case TGSI_FILE_CONSTANT:
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src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0);
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break;
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case TGSI_FILE_IMMEDIATE:
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src = vpc->imm[fsrc->SrcRegister.Index];
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break;
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case TGSI_FILE_TEMPORARY:
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if (vpc->high_temp < fsrc->SrcRegister.Index)
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vpc->high_temp = fsrc->SrcRegister.Index;
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src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index);
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break;
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default:
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NOUVEAU_ERR("bad src file\n");
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break;
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}
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src.abs = fsrc->SrcRegisterExtMod.Absolute;
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src.negate = fsrc->SrcRegister.Negate;
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src.swz[0] = fsrc->SrcRegister.SwizzleX;
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src.swz[1] = fsrc->SrcRegister.SwizzleY;
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src.swz[2] = fsrc->SrcRegister.SwizzleZ;
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src.swz[3] = fsrc->SrcRegister.SwizzleW;
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return src;
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}
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static INLINE struct nv30_sreg
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tgsi_dst(struct nv30_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
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struct nv30_sreg dst;
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switch (fdst->DstRegister.File) {
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case TGSI_FILE_OUTPUT:
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dst = nv30_sr(NV30SR_OUTPUT,
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vpc->output_map[fdst->DstRegister.Index]);
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break;
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case TGSI_FILE_TEMPORARY:
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dst = nv30_sr(NV30SR_TEMP, fdst->DstRegister.Index);
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if (vpc->high_temp < dst.index)
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vpc->high_temp = dst.index;
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break;
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default:
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NOUVEAU_ERR("bad dst file\n");
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break;
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}
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return dst;
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}
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static INLINE int
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tgsi_mask(uint tgsi)
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{
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int mask = 0;
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if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X;
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if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y;
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if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z;
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if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W;
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return mask;
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}
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static boolean
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nv30_vertprog_parse_instruction(struct nv30_vpc *vpc,
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const struct tgsi_full_instruction *finst)
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{
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struct nv30_sreg src[3], dst, tmp;
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struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0);
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int mask;
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int ai = -1, ci = -1;
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int i;
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if (finst->Instruction.Opcode == TGSI_OPCODE_END)
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return TRUE;
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vpc->temp_temp_count = 0;
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for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
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const struct tgsi_full_src_register *fsrc;
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fsrc = &finst->FullSrcRegisters[i];
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if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
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src[i] = tgsi_src(vpc, fsrc);
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}
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}
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for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
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const struct tgsi_full_src_register *fsrc;
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fsrc = &finst->FullSrcRegisters[i];
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switch (fsrc->SrcRegister.File) {
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case TGSI_FILE_INPUT:
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if (ai == -1 || ai == fsrc->SrcRegister.Index) {
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ai = fsrc->SrcRegister.Index;
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src[i] = tgsi_src(vpc, fsrc);
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} else {
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src[i] = temp(vpc);
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arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
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tgsi_src(vpc, fsrc), none, none);
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}
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break;
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/*XXX: index comparison is broken now that consts come from
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* two different register files.
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*/
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case TGSI_FILE_CONSTANT:
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case TGSI_FILE_IMMEDIATE:
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if (ci == -1 || ci == fsrc->SrcRegister.Index) {
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ci = fsrc->SrcRegister.Index;
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src[i] = tgsi_src(vpc, fsrc);
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} else {
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src[i] = temp(vpc);
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arith(vpc, 0, OP_MOV, src[i], MASK_ALL,
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tgsi_src(vpc, fsrc), none, none);
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}
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break;
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case TGSI_FILE_TEMPORARY:
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/* handled above */
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break;
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default:
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NOUVEAU_ERR("bad src file\n");
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return FALSE;
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}
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}
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dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
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mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
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switch (finst->Instruction.Opcode) {
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case TGSI_OPCODE_ABS:
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arith(vpc, 0, OP_MOV, dst, mask, abs(src[0]), none, none);
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break;
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case TGSI_OPCODE_ADD:
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arith(vpc, 0, OP_ADD, dst, mask, src[0], none, src[1]);
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break;
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case TGSI_OPCODE_ARL:
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arith(vpc, 0, OP_ARL, dst, mask, src[0], none, none);
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break;
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case TGSI_OPCODE_DP3:
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arith(vpc, 0, OP_DP3, dst, mask, src[0], src[1], none);
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break;
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case TGSI_OPCODE_DP4:
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arith(vpc, 0, OP_DP4, dst, mask, src[0], src[1], none);
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break;
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case TGSI_OPCODE_DPH:
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arith(vpc, 0, OP_DPH, dst, mask, src[0], src[1], none);
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break;
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case TGSI_OPCODE_DST:
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arith(vpc, 0, OP_DST, dst, mask, src[0], src[1], none);
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break;
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case TGSI_OPCODE_EX2:
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arith(vpc, 1, OP_EX2, dst, mask, none, none, src[0]);
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break;
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case TGSI_OPCODE_EXP:
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arith(vpc, 1, OP_EXP, dst, mask, none, none, src[0]);
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break;
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case TGSI_OPCODE_FLR:
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arith(vpc, 0, OP_FLR, dst, mask, src[0], none, none);
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break;
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case TGSI_OPCODE_FRC:
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arith(vpc, 0, OP_FRC, dst, mask, src[0], none, none);
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break;
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case TGSI_OPCODE_LG2:
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arith(vpc, 1, OP_LG2, dst, mask, none, none, src[0]);
|
||||
break;
|
||||
case TGSI_OPCODE_LIT:
|
||||
arith(vpc, 1, OP_LIT, dst, mask, none, none, src[0]);
|
||||
break;
|
||||
case TGSI_OPCODE_LOG:
|
||||
arith(vpc, 1, OP_LOG, dst, mask, none, none, src[0]);
|
||||
break;
|
||||
case TGSI_OPCODE_MAD:
|
||||
arith(vpc, 0, OP_MAD, dst, mask, src[0], src[1], src[2]);
|
||||
break;
|
||||
case TGSI_OPCODE_MAX:
|
||||
arith(vpc, 0, OP_MAX, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_MIN:
|
||||
arith(vpc, 0, OP_MIN, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_MOV:
|
||||
arith(vpc, 0, OP_MOV, dst, mask, src[0], none, none);
|
||||
break;
|
||||
case TGSI_OPCODE_MUL:
|
||||
arith(vpc, 0, OP_MUL, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_POW:
|
||||
tmp = temp(vpc);
|
||||
arith(vpc, 1, OP_LG2, tmp, MASK_X, none, none,
|
||||
swz(src[0], X, X, X, X));
|
||||
arith(vpc, 0, OP_MUL, tmp, MASK_X, swz(tmp, X, X, X, X),
|
||||
swz(src[1], X, X, X, X), none);
|
||||
arith(vpc, 1, OP_EX2, dst, mask, none, none,
|
||||
swz(tmp, X, X, X, X));
|
||||
break;
|
||||
case TGSI_OPCODE_RCP:
|
||||
arith(vpc, 1, OP_RCP, dst, mask, none, none, src[0]);
|
||||
break;
|
||||
case TGSI_OPCODE_RET:
|
||||
break;
|
||||
case TGSI_OPCODE_RSQ:
|
||||
arith(vpc, 1, OP_RSQ, dst, mask, none, none, src[0]);
|
||||
break;
|
||||
case TGSI_OPCODE_SGE:
|
||||
arith(vpc, 0, OP_SGE, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_SGT:
|
||||
arith(vpc, 0, OP_SGT, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_SLT:
|
||||
arith(vpc, 0, OP_SLT, dst, mask, src[0], src[1], none);
|
||||
break;
|
||||
case TGSI_OPCODE_SUB:
|
||||
arith(vpc, 0, OP_ADD, dst, mask, src[0], none, neg(src[1]));
|
||||
break;
|
||||
case TGSI_OPCODE_XPD:
|
||||
tmp = temp(vpc);
|
||||
arith(vpc, 0, OP_MUL, tmp, mask,
|
||||
swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
|
||||
arith(vpc, 0, OP_MAD, dst, (mask & ~MASK_W),
|
||||
swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
|
||||
neg(tmp));
|
||||
break;
|
||||
default:
|
||||
NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static boolean
|
||||
nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc,
|
||||
const struct tgsi_full_declaration *fdec)
|
||||
{
|
||||
int hw;
|
||||
|
||||
switch (fdec->Semantic.SemanticName) {
|
||||
case TGSI_SEMANTIC_POSITION:
|
||||
hw = NV30_VP_INST_DEST_POS;
|
||||
break;
|
||||
case TGSI_SEMANTIC_COLOR:
|
||||
if (fdec->Semantic.SemanticIndex == 0) {
|
||||
hw = NV30_VP_INST_DEST_COL0;
|
||||
} else
|
||||
if (fdec->Semantic.SemanticIndex == 1) {
|
||||
hw = NV30_VP_INST_DEST_COL1;
|
||||
} else {
|
||||
NOUVEAU_ERR("bad colour semantic index\n");
|
||||
return FALSE;
|
||||
}
|
||||
break;
|
||||
case TGSI_SEMANTIC_BCOLOR:
|
||||
if (fdec->Semantic.SemanticIndex == 0) {
|
||||
hw = NV30_VP_INST_DEST_BFC0;
|
||||
} else
|
||||
if (fdec->Semantic.SemanticIndex == 1) {
|
||||
hw = NV30_VP_INST_DEST_BFC1;
|
||||
} else {
|
||||
NOUVEAU_ERR("bad bcolour semantic index\n");
|
||||
return FALSE;
|
||||
}
|
||||
break;
|
||||
case TGSI_SEMANTIC_FOG:
|
||||
hw = NV30_VP_INST_DEST_FOGC;
|
||||
break;
|
||||
case TGSI_SEMANTIC_PSIZE:
|
||||
hw = NV30_VP_INST_DEST_PSZ;
|
||||
break;
|
||||
case TGSI_SEMANTIC_GENERIC:
|
||||
if (fdec->Semantic.SemanticIndex <= 7) {
|
||||
hw = NV30_VP_INST_DEST_TC(fdec->Semantic.SemanticIndex);
|
||||
} else {
|
||||
NOUVEAU_ERR("bad generic semantic index\n");
|
||||
return FALSE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
NOUVEAU_ERR("bad output semantic\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
vpc->output_map[fdec->DeclarationRange.First] = hw;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static boolean
|
||||
nv30_vertprog_prepare(struct nv30_vpc *vpc)
|
||||
{
|
||||
struct tgsi_parse_context p;
|
||||
int nr_imm = 0;
|
||||
|
||||
tgsi_parse_init(&p, vpc->vp->pipe.tokens);
|
||||
while (!tgsi_parse_end_of_tokens(&p)) {
|
||||
const union tgsi_full_token *tok = &p.FullToken;
|
||||
|
||||
tgsi_parse_token(&p);
|
||||
switch(tok->Token.Type) {
|
||||
case TGSI_TOKEN_TYPE_IMMEDIATE:
|
||||
nr_imm++;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
tgsi_parse_free(&p);
|
||||
|
||||
if (nr_imm) {
|
||||
vpc->imm = CALLOC(nr_imm, sizeof(struct nv30_sreg));
|
||||
assert(vpc->imm);
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
static void
|
||||
nv30_vertprog_translate(struct nv30_context *nv30,
|
||||
struct nv30_vertex_program *vp)
|
||||
{
|
||||
struct tgsi_parse_context parse;
|
||||
struct nv30_vpc *vpc = NULL;
|
||||
|
||||
tgsi_dump(vp->pipe.tokens,0);
|
||||
|
||||
vpc = CALLOC(1, sizeof(struct nv30_vpc));
|
||||
if (!vpc)
|
||||
return;
|
||||
vpc->vp = vp;
|
||||
vpc->high_temp = -1;
|
||||
|
||||
if (!nv30_vertprog_prepare(vpc)) {
|
||||
FREE(vpc);
|
||||
return;
|
||||
}
|
||||
|
||||
tgsi_parse_init(&parse, vp->pipe.tokens);
|
||||
|
||||
while (!tgsi_parse_end_of_tokens(&parse)) {
|
||||
tgsi_parse_token(&parse);
|
||||
|
||||
switch (parse.FullToken.Token.Type) {
|
||||
case TGSI_TOKEN_TYPE_DECLARATION:
|
||||
{
|
||||
const struct tgsi_full_declaration *fdec;
|
||||
fdec = &parse.FullToken.FullDeclaration;
|
||||
switch (fdec->Declaration.File) {
|
||||
case TGSI_FILE_OUTPUT:
|
||||
if (!nv30_vertprog_parse_decl_output(vpc, fdec))
|
||||
goto out_err;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case TGSI_TOKEN_TYPE_IMMEDIATE:
|
||||
{
|
||||
const struct tgsi_full_immediate *imm;
|
||||
|
||||
imm = &parse.FullToken.FullImmediate;
|
||||
assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
|
||||
// assert(imm->Immediate.Size == 4);
|
||||
vpc->imm[vpc->nr_imm++] =
|
||||
constant(vpc, -1,
|
||||
imm->u.ImmediateFloat32[0].Float,
|
||||
imm->u.ImmediateFloat32[1].Float,
|
||||
imm->u.ImmediateFloat32[2].Float,
|
||||
imm->u.ImmediateFloat32[3].Float);
|
||||
}
|
||||
break;
|
||||
case TGSI_TOKEN_TYPE_INSTRUCTION:
|
||||
{
|
||||
const struct tgsi_full_instruction *finst;
|
||||
finst = &parse.FullToken.FullInstruction;
|
||||
if (!nv30_vertprog_parse_instruction(vpc, finst))
|
||||
goto out_err;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
vp->insns[vp->nr_insns - 1].data[3] |= NV30_VP_INST_LAST;
|
||||
vp->translated = TRUE;
|
||||
out_err:
|
||||
tgsi_parse_free(&parse);
|
||||
FREE(vpc);
|
||||
}
|
||||
|
||||
static boolean
|
||||
nv30_vertprog_validate(struct nv30_context *nv30)
|
||||
{
|
||||
struct nouveau_winsys *nvws = nv30->nvws;
|
||||
struct pipe_winsys *ws = nv30->pipe.winsys;
|
||||
struct nouveau_grobj *rankine = nv30->screen->rankine;
|
||||
struct nv30_vertex_program *vp;
|
||||
struct pipe_buffer *constbuf;
|
||||
boolean upload_code = FALSE, upload_data = FALSE;
|
||||
int i;
|
||||
|
||||
vp = nv30->vertprog;
|
||||
constbuf = nv30->constbuf[PIPE_SHADER_VERTEX];
|
||||
|
||||
/* Translate TGSI shader into hw bytecode */
|
||||
if (!vp->translated) {
|
||||
nv30_vertprog_translate(nv30, vp);
|
||||
if (!vp->translated)
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Allocate hw vtxprog exec slots */
|
||||
if (!vp->exec) {
|
||||
struct nouveau_resource *heap = nv30->screen->vp_exec_heap;
|
||||
struct nouveau_stateobj *so;
|
||||
uint vplen = vp->nr_insns;
|
||||
|
||||
if (nvws->res_alloc(heap, vplen, vp, &vp->exec)) {
|
||||
while (heap->next && heap->size < vplen) {
|
||||
struct nv30_vertex_program *evict;
|
||||
|
||||
evict = heap->next->priv;
|
||||
nvws->res_free(&evict->exec);
|
||||
}
|
||||
|
||||
if (nvws->res_alloc(heap, vplen, vp, &vp->exec))
|
||||
assert(0);
|
||||
}
|
||||
|
||||
so = so_new(2, 0);
|
||||
so_method(so, rankine, NV34TCL_VP_START_FROM_ID, 1);
|
||||
so_data (so, vp->exec->start);
|
||||
so_ref(so, &vp->so);
|
||||
|
||||
upload_code = TRUE;
|
||||
}
|
||||
|
||||
/* Allocate hw vtxprog const slots */
|
||||
if (vp->nr_consts && !vp->data) {
|
||||
struct nouveau_resource *heap = nv30->screen->vp_data_heap;
|
||||
|
||||
if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data)) {
|
||||
while (heap->next && heap->size < vp->nr_consts) {
|
||||
struct nv30_vertex_program *evict;
|
||||
|
||||
evict = heap->next->priv;
|
||||
nvws->res_free(&evict->data);
|
||||
}
|
||||
|
||||
if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data))
|
||||
assert(0);
|
||||
}
|
||||
|
||||
/*XXX: handle this some day */
|
||||
assert(vp->data->start >= vp->data_start_min);
|
||||
|
||||
upload_data = TRUE;
|
||||
if (vp->data_start != vp->data->start)
|
||||
upload_code = TRUE;
|
||||
}
|
||||
|
||||
/* If exec or data segments moved we need to patch the program to
|
||||
* fixup offsets and register IDs.
|
||||
*/
|
||||
if (vp->exec_start != vp->exec->start) {
|
||||
for (i = 0; i < vp->nr_insns; i++) {
|
||||
struct nv30_vertex_program_exec *vpi = &vp->insns[i];
|
||||
|
||||
if (vpi->has_branch_offset) {
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
vp->exec_start = vp->exec->start;
|
||||
}
|
||||
|
||||
if (vp->nr_consts && vp->data_start != vp->data->start) {
|
||||
for (i = 0; i < vp->nr_insns; i++) {
|
||||
struct nv30_vertex_program_exec *vpi = &vp->insns[i];
|
||||
|
||||
if (vpi->const_index >= 0) {
|
||||
vpi->data[1] &= ~NV30_VP_INST_CONST_SRC_MASK;
|
||||
vpi->data[1] |=
|
||||
(vpi->const_index + vp->data->start) <<
|
||||
NV30_VP_INST_CONST_SRC_SHIFT;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
vp->data_start = vp->data->start;
|
||||
}
|
||||
|
||||
/* Update + Upload constant values */
|
||||
if (vp->nr_consts) {
|
||||
float *map = NULL;
|
||||
|
||||
if (constbuf) {
|
||||
map = ws->buffer_map(ws, constbuf,
|
||||
PIPE_BUFFER_USAGE_CPU_READ);
|
||||
}
|
||||
|
||||
for (i = 0; i < vp->nr_consts; i++) {
|
||||
struct nv30_vertex_program_data *vpd = &vp->consts[i];
|
||||
|
||||
if (vpd->index >= 0) {
|
||||
if (!upload_data &&
|
||||
!memcmp(vpd->value, &map[vpd->index * 4],
|
||||
4 * sizeof(float)))
|
||||
continue;
|
||||
memcpy(vpd->value, &map[vpd->index * 4],
|
||||
4 * sizeof(float));
|
||||
}
|
||||
|
||||
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_CONST_ID, 5);
|
||||
OUT_RING (i + vp->data->start);
|
||||
OUT_RINGp ((uint32_t *)vpd->value, 4);
|
||||
}
|
||||
|
||||
if (constbuf) {
|
||||
ws->buffer_unmap(ws, constbuf);
|
||||
}
|
||||
}
|
||||
|
||||
/* Upload vtxprog */
|
||||
if (upload_code) {
|
||||
#if 0
|
||||
for (i = 0; i < vp->nr_insns; i++) {
|
||||
NOUVEAU_MSG("VP inst %d: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||||
i, vp->insns[i].data[0], vp->insns[i].data[1],
|
||||
vp->insns[i].data[2], vp->insns[i].data[3]);
|
||||
}
|
||||
#endif
|
||||
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_FROM_ID, 1);
|
||||
OUT_RING (vp->exec->start);
|
||||
for (i = 0; i < vp->nr_insns; i++) {
|
||||
BEGIN_RING(rankine, NV34TCL_VP_UPLOAD_INST(0), 4);
|
||||
OUT_RINGp (vp->insns[i].data, 4);
|
||||
}
|
||||
}
|
||||
|
||||
if (vp->so != nv30->state.hw[NV30_STATE_VERTPROG]) {
|
||||
so_ref(vp->so, &nv30->state.hw[NV30_STATE_VERTPROG]);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
void
|
||||
nv30_vertprog_destroy(struct nv30_context *nv30, struct nv30_vertex_program *vp)
|
||||
{
|
||||
struct nouveau_winsys *nvws = nv30->screen->nvws;
|
||||
|
||||
vp->translated = FALSE;
|
||||
|
||||
if (vp->nr_insns) {
|
||||
FREE(vp->insns);
|
||||
vp->insns = NULL;
|
||||
vp->nr_insns = 0;
|
||||
}
|
||||
|
||||
if (vp->nr_consts) {
|
||||
FREE(vp->consts);
|
||||
vp->consts = NULL;
|
||||
vp->nr_consts = 0;
|
||||
}
|
||||
|
||||
nvws->res_free(&vp->exec);
|
||||
vp->exec_start = 0;
|
||||
nvws->res_free(&vp->data);
|
||||
vp->data_start = 0;
|
||||
vp->data_start_min = 0;
|
||||
|
||||
vp->ir = vp->or = 0;
|
||||
so_ref(NULL, &vp->so);
|
||||
}
|
||||
|
||||
struct nv30_state_entry nv30_state_vertprog = {
|
||||
.validate = nv30_vertprog_validate,
|
||||
.dirty = {
|
||||
.pipe = NV30_NEW_VERTPROG /*| NV30_NEW_UCP*/,
|
||||
.hw = NV30_STATE_VERTPROG,
|
||||
}
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue