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panfrost/midgard: Hoist mask field
Share a single mask field in midgard_instruction with a unified format, rather than using separate masks for each instruction tag with hardware-specific formats. Eliminates quite a bit of duplicated code and will enable vec8/vec16 masks as well (which don't map as cleanly to the hardware as we might like). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig
parent
e69cf1fed9
commit
f8b18a4277
7 changed files with 70 additions and 80 deletions
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@ -120,6 +120,11 @@ typedef struct midgard_instruction {
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bool writeout;
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bool prepacked_branch;
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/* Masks in a saneish format. One bit per channel, not packed fancy.
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* Use this instead of the op specific ones, and switch over at emit
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* time */
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uint16_t mask;
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union {
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midgard_load_store_word load_store;
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midgard_vector_alu alu;
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@ -398,6 +403,7 @@ v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
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{
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midgard_instruction ins = {
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.type = TAG_ALU_4,
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.mask = 0xF,
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.ssa_args = {
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.src0 = SSA_UNUSED_1,
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.src1 = src,
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@ -408,7 +414,6 @@ v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.outmod = midgard_outmod_int_wrap,
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.mask = 0xFF,
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.src1 = vector_alu_srco_unsigned(zero_alu_src),
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.src2 = vector_alu_srco_unsigned(mod)
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},
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@ -217,13 +217,11 @@ struct mir_op_props {
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/* This file is common, so don't define the tables themselves. #include
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* midgard_op.h if you need that, or edit midgard_ops.c directly */
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/* Duplicate bits to convert standard 4-bit writemask to duplicated 8-bit
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* format (or do the inverse). The 8-bit format only really matters for
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* int8, as far as I know, where performance can be improved by using a
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* vec8 output */
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/* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
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* which is used for 32-bit vector units */
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static inline unsigned
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expand_writemask(unsigned mask)
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expand_writemask_32(unsigned mask)
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{
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unsigned o = 0;
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@ -234,19 +232,6 @@ expand_writemask(unsigned mask)
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return o;
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}
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static inline unsigned
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squeeze_writemask(unsigned mask)
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{
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unsigned o = 0;
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for (int i = 0; i < 4; ++i)
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if (mask & (3 << (2 * i)))
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o |= (1 << i);
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return o;
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}
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/* Coerce structs to integer */
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static inline unsigned
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@ -88,6 +88,7 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor)
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static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
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midgard_instruction i = { \
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.type = TAG_LOAD_STORE_4, \
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.mask = 0xF, \
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.ssa_args = { \
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.rname = ssa, \
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.uname = -1, \
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@ -95,7 +96,6 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor)
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}, \
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.load_store = { \
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.op = midgard_op_##name, \
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.mask = 0xF, \
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.swizzle = SWIZZLE_XYZW, \
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.address = address \
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} \
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@ -596,6 +596,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co
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/* We need to set the conditional as close as possible */
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.precede_break = true,
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.unit = for_branch ? UNIT_SMUL : UNIT_SADD,
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.mask = 1 << COMPONENT_W,
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.ssa_args = {
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.src0 = condition,
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@ -608,7 +609,6 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co
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.outmod = midgard_outmod_int_wrap,
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.mask = (0x3 << 6), /* w */
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(alu_src)
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},
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@ -637,6 +637,7 @@ emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
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midgard_instruction ins = {
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.type = TAG_ALU_4,
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.precede_break = true,
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.mask = mask_of(nr_comp),
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.ssa_args = {
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.src0 = condition,
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.src1 = condition,
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@ -647,7 +648,6 @@ emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp)
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.outmod = midgard_outmod_int_wrap,
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.mask = expand_writemask(mask_of(nr_comp)),
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.src1 = vector_alu_srco_unsigned(alu_src),
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.src2 = vector_alu_srco_unsigned(alu_src)
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},
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@ -668,6 +668,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
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midgard_instruction ins = {
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.type = TAG_ALU_4,
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.mask = 1 << COMPONENT_W,
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.ssa_args = {
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.src0 = SSA_UNUSED_1,
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.src1 = offset,
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@ -678,7 +679,6 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
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.outmod = midgard_outmod_int_wrap,
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.reg_mode = midgard_reg_mode_32,
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.dest_override = midgard_dest_override_none,
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.mask = (0x3 << 6), /* w */
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.src1 = vector_alu_srco_unsigned(zero_alu_src),
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.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx)
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},
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@ -1062,15 +1062,14 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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bool is_int = midgard_is_integer_op(op);
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ins.mask = mask_of(nr_components);
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midgard_vector_alu alu = {
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.op = op,
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.reg_mode = reg_mode,
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.dest_override = dest_override,
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.outmod = outmod,
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/* Writemask only valid for non-SSA NIR */
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.mask = expand_writemask(mask_of(nr_components)),
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.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)),
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.src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)),
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};
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@ -1078,7 +1077,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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/* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
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if (!is_ssa)
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alu.mask &= expand_writemask(instr->dest.write_mask);
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ins.mask &= instr->dest.write_mask;
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ins.alu = alu;
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@ -1123,15 +1122,16 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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uint8_t original_swizzle[4];
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memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle));
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unsigned orig_mask = ins.mask;
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for (int i = 0; i < nr_components; ++i) {
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/* Mask the associated component, dropping the
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* instruction if needed */
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ins.alu.mask = (0x3) << (2 * i);
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ins.alu.mask &= alu.mask;
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ins.mask = 1 << i;
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ins.mask &= orig_mask;
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if (!ins.alu.mask)
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if (!ins.mask)
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continue;
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for (int j = 0; j < 4; ++j)
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@ -1203,7 +1203,7 @@ emit_varying_read(
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/* TODO: swizzle, mask */
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midgard_instruction ins = m_ld_vary_32(dest, offset);
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ins.load_store.mask = mask_of(nr_comp);
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ins.mask = mask_of(nr_comp);
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ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component);
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midgard_varying_parameter p = {
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@ -1342,7 +1342,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
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} else if (ctx->stage == MESA_SHADER_VERTEX) {
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midgard_instruction ins = m_ld_attr_32(reg, offset);
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ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
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ins.load_store.mask = mask_of(nr_comp);
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ins.mask = mask_of(nr_comp);
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/* Use the type appropriate load */
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switch (t) {
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@ -1574,6 +1574,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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/* No helper to build texture words -- we do it all here */
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midgard_instruction ins = {
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.type = TAG_TEXTURE_4,
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.mask = 0xF,
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.texture = {
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.op = midgard_texop,
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.format = midgard_tex_format(instr->sampler_dim),
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@ -1582,7 +1583,6 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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/* TODO: Regalloc it in */
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.swizzle = SWIZZLE_XYZW,
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.mask = 0xF,
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/* TODO: half */
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.in_reg_full = 1,
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@ -1616,7 +1616,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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midgard_instruction st = m_st_cubemap_coords(reg, 0);
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st.load_store.unknown = 0x24; /* XXX: What is this? */
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st.load_store.mask = 0x3; /* xy */
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st.mask = 0x3; /* xy */
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st.load_store.swizzle = alu_src.swizzle;
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emit_mir_instruction(ctx, st);
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@ -1625,7 +1625,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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ins.texture.in_reg_swizzle = alu_src.swizzle = swizzle_of(nr_comp);
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midgard_instruction mov = v_mov(index, alu_src, reg);
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mov.alu.mask = expand_writemask(mask_of(nr_comp));
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mov.mask = mask_of(nr_comp);
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emit_mir_instruction(ctx, mov);
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if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) {
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@ -1642,7 +1642,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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zero.ssa_args.inline_constant = true;
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zero.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
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zero.has_constants = true;
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zero.alu.mask = ~mov.alu.mask;
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zero.mask = ~mov.mask;
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emit_mir_instruction(ctx, zero);
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ins.texture.in_reg_swizzle = SWIZZLE_XYZZ;
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@ -1673,7 +1673,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
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alu_src.swizzle = SWIZZLE_XXXX;
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midgard_instruction mov = v_mov(index, alu_src, reg);
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mov.alu.mask = expand_writemask(1 << COMPONENT_W);
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mov.mask = 1 << COMPONENT_W;
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emit_mir_instruction(ctx, mov);
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ins.texture.lod_register = true;
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@ -1969,7 +1969,7 @@ embedded_to_inline_constant(compiler_context *ctx)
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uint32_t value = cons[component];
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bool is_vector = false;
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unsigned mask = effective_writemask(&ins->alu);
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unsigned mask = effective_writemask(&ins->alu, ins->mask);
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for (int c = 1; c < 4; ++c) {
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/* We only care if this component is actually used */
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@ -2097,13 +2097,12 @@ mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
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static bool
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mir_nontrivial_source2_mod(midgard_instruction *ins)
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{
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unsigned mask = squeeze_writemask(ins->alu.mask);
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bool is_int = midgard_is_integer_op(ins->alu.op);
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midgard_vector_alu_src src2 =
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vector_alu_from_unsigned(ins->alu.src2);
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return mir_nontrivial_mod(src2, is_int, mask);
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return mir_nontrivial_mod(src2, is_int, ins->mask);
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}
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static bool
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@ -2250,7 +2249,7 @@ midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
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if (v->ssa_args.dest == from) {
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/* We don't want to track partial writes ... */
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if (v->alu.mask == 0xF) {
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if (v->mask == 0xF) {
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v->ssa_args.dest = to;
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eliminated = true;
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}
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@ -29,15 +29,11 @@
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* this, we just demote vector ALU payloads to scalar. */
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static int
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component_from_mask(unsigned mask, bool full)
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component_from_mask(unsigned mask)
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{
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for (int c = 0; c < 8; ++c) {
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if (mask & (1 << c))
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return c;
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/* Full uses every other bit */
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if (full)
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c++;
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}
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assert(0);
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@ -102,9 +98,15 @@ vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
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.unknown = 0,
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.outmod = v.outmod,
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.output_full = is_full,
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.output_component = component_from_mask(v.mask, is_full),
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.output_component = component_from_mask(ins->mask),
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};
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/* Full components are physically spaced out */
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if (is_full) {
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assert(s.output_component < 4);
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s.output_component <<= 1;
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}
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/* Inline constant is passed along rather than trying to extract it
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* from v */
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@ -156,6 +158,11 @@ emit_alu_bundle(compiler_context *ctx,
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midgard_scalar_alu scalarized;
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if (ins->unit & UNITS_ANY_VECTOR) {
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if (ins->alu.reg_mode == midgard_reg_mode_32)
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ins->alu.mask = expand_writemask_32(ins->mask);
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else
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ins->alu.mask = ins->mask;
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size = sizeof(midgard_vector_alu);
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source = &ins->alu;
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} else if (ins->unit == ALU_ENAB_BR_COMPACT) {
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@ -209,6 +216,13 @@ emit_binary_bundle(compiler_context *ctx,
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uint64_t current64, next64 = LDST_NOP;
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/* Copy masks */
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for (unsigned i = 0; i < bundle->instruction_count; ++i) {
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bundle->instructions[i]->load_store.mask =
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bundle->instructions[i]->mask;
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}
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memcpy(¤t64, &bundle->instructions[0]->load_store, sizeof(current64));
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if (bundle->instruction_count == 2)
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@ -236,6 +250,7 @@ emit_binary_bundle(compiler_context *ctx,
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ins->texture.type = bundle->tag;
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ins->texture.next_type = next_tag;
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ins->texture.mask = ins->mask;
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ctx->texture_op_count--;
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@ -53,8 +53,9 @@ midgard_is_integer_out_op(int op)
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}
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/* Determines effective writemask, taking quirks and expansion into account */
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static inline unsigned
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effective_writemask(midgard_vector_alu *alu)
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effective_writemask(midgard_vector_alu *alu, unsigned existing_mask)
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{
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/* Channel count is off-by-one to fit in two-bits (0 channel makes no
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* sense) */
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@ -66,9 +67,7 @@ effective_writemask(midgard_vector_alu *alu)
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if (channel_count)
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return (1 << channel_count) - 1;
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/* Otherwise, just squeeze the existing mask */
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return squeeze_writemask(alu->mask);
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}
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return existing_mask;
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};
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@ -293,16 +293,7 @@ allocate_registers(compiler_context *ctx)
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if (ins->ssa_args.dest < 0) continue;
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if (ins->ssa_args.dest >= SSA_FIXED_MINIMUM) continue;
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/* Default to vec4 if we're not sure */
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int mask = 0xF;
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if (ins->type == TAG_ALU_4)
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mask = squeeze_writemask(ins->alu.mask);
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else if (ins->type == TAG_LOAD_STORE_4)
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mask = ins->load_store.mask;
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int class = util_logbase2(mask) + 1;
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int class = util_logbase2(ins->mask) + 1;
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/* Use the largest class if there's ambiguity, this
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* handles partial writes */
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@ -430,16 +421,16 @@ install_registers_instr(
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struct phys_reg src2 = index_to_reg(ctx, g, adjusted_src);
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struct phys_reg dest = index_to_reg(ctx, g, args.dest);
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unsigned mask = squeeze_writemask(ins->alu.mask);
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ins->alu.mask = expand_writemask(compose_writemask(mask, dest));
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unsigned uncomposed_mask = ins->mask;
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ins->mask = compose_writemask(uncomposed_mask, dest);
|
||||
|
||||
/* Adjust the dest mask if necessary. Mostly this is a no-op
|
||||
* but it matters for dot products */
|
||||
dest.mask = effective_writemask(&ins->alu);
|
||||
dest.mask = effective_writemask(&ins->alu, ins->mask);
|
||||
|
||||
midgard_vector_alu_src mod1 =
|
||||
vector_alu_from_unsigned(ins->alu.src1);
|
||||
mod1.swizzle = compose_swizzle(mod1.swizzle, mask, src1, dest);
|
||||
mod1.swizzle = compose_swizzle(mod1.swizzle, uncomposed_mask, src1, dest);
|
||||
ins->alu.src1 = vector_alu_srco_unsigned(mod1);
|
||||
|
||||
ins->registers.src1_reg = src1.reg;
|
||||
|
|
@ -461,7 +452,7 @@ install_registers_instr(
|
|||
midgard_vector_alu_src mod2 =
|
||||
vector_alu_from_unsigned(ins->alu.src2);
|
||||
mod2.swizzle = compose_swizzle(
|
||||
mod2.swizzle, mask, src2, dest);
|
||||
mod2.swizzle, uncomposed_mask, src2, dest);
|
||||
ins->alu.src2 = vector_alu_srco_unsigned(mod2);
|
||||
|
||||
ins->registers.src2_reg = src2.reg;
|
||||
|
|
@ -490,8 +481,8 @@ install_registers_instr(
|
|||
ins->load_store.swizzle, 0xF,
|
||||
default_phys_reg(0), src);
|
||||
|
||||
ins->load_store.mask = compose_writemask(
|
||||
ins->load_store.mask, src);
|
||||
ins->mask = compose_writemask(
|
||||
ins->mask, src);
|
||||
}
|
||||
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -44,17 +44,13 @@ swizzle_to_access_mask(unsigned swizzle)
|
|||
/* Does the mask cover more than a scalar? */
|
||||
|
||||
static bool
|
||||
is_single_component_mask(unsigned mask, bool full)
|
||||
is_single_component_mask(unsigned mask)
|
||||
{
|
||||
int components = 0;
|
||||
|
||||
for (int c = 0; c < 8; ++c) {
|
||||
if (mask & (1 << c))
|
||||
components++;
|
||||
|
||||
/* Full uses 2-bit components */
|
||||
if (full)
|
||||
c++;
|
||||
}
|
||||
|
||||
return components == 1;
|
||||
|
|
@ -72,7 +68,7 @@ can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
|
|||
|
||||
/* Figure out where exactly we wrote to */
|
||||
int source = first->ssa_args.dest;
|
||||
int source_mask = first->type == TAG_ALU_4 ? squeeze_writemask(first->alu.mask) : 0xF;
|
||||
int source_mask = first->mask;
|
||||
|
||||
/* As long as the second doesn't read from the first, we're okay */
|
||||
if (second->ssa_args.src0 == source) {
|
||||
|
|
@ -98,9 +94,8 @@ can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
|
|||
|
||||
if (second->ssa_args.dest == source) {
|
||||
/* ...but only if the components overlap */
|
||||
int dest_mask = second->type == TAG_ALU_4 ? squeeze_writemask(second->alu.mask) : 0xF;
|
||||
|
||||
if (dest_mask & source_mask)
|
||||
if (second->mask & source_mask)
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -198,13 +193,14 @@ schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction
|
|||
|
||||
bool vectorable = units & UNITS_ANY_VECTOR;
|
||||
bool scalarable = units & UNITS_SCALAR;
|
||||
bool full = ains->alu.reg_mode == midgard_reg_mode_32;
|
||||
bool could_scalar = is_single_component_mask(ains->alu.mask, full);
|
||||
bool vector = vectorable && !(could_scalar && scalarable);
|
||||
bool could_scalar = is_single_component_mask(ains->mask);
|
||||
|
||||
/* Only 16/32-bit can run on a scalar unit */
|
||||
could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
|
||||
could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
|
||||
could_scalar &= ains->alu.dest_override == midgard_dest_override_none;
|
||||
|
||||
bool vector = vectorable && !(could_scalar && scalarable);
|
||||
|
||||
/* TODO: Check ahead-of-time for other scalar
|
||||
* hazards that otherwise get aborted out */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue