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radv: move queue related cmd buffer state to a new struct
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41107>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
3f5d54ab8c
commit
f8aed0793b
4 changed files with 76 additions and 87 deletions
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@ -1281,23 +1281,12 @@ radv_reset_cmd_buffer(struct vk_command_buffer *vk_cmd_buffer, UNUSED VkCommandB
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radv_rra_accel_struct_buffers_unref(device, cmd_buffer->accel_struct_buffers);
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cmd_buffer->push_constant_stages = 0;
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cmd_buffer->scratch_size_per_wave_needed = 0;
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cmd_buffer->scratch_waves_wanted = 0;
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cmd_buffer->compute_scratch_size_per_wave_needed = 0;
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cmd_buffer->compute_scratch_waves_wanted = 0;
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cmd_buffer->esgs_ring_size_needed = 0;
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cmd_buffer->gsvs_ring_size_needed = 0;
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cmd_buffer->tess_rings_needed = false;
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cmd_buffer->task_rings_needed = false;
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cmd_buffer->mesh_scratch_ring_needed = false;
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cmd_buffer->gds_needed = false;
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cmd_buffer->gds_oa_needed = false;
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cmd_buffer->sample_positions_needed = false;
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cmd_buffer->gang.sem.leader_value = 0;
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cmd_buffer->gang.sem.emitted_leader_value = 0;
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cmd_buffer->gang.sem.va = 0;
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cmd_buffer->shader_upload_seq = 0;
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memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));
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memset(&cmd_buffer->queue_state, 0, sizeof(cmd_buffer->queue_state));
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if (cmd_buffer->upload.upload_bo)
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radv_cs_add_buffer(device->ws, cs->b, cmd_buffer->upload.upload_bo);
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@ -8429,7 +8418,7 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer)
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* we leave the IB, otherwise another process might overwrite
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* it while our shaders are busy.
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*/
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if (cmd_buffer->gds_needed)
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if (cmd_buffer->queue_state.gds_needed)
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cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
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}
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@ -8679,7 +8668,7 @@ radv_bind_pre_rast_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
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if (pdev->use_ngg_streamout && pdev->info.gfx_level < GFX12) {
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/* GFX11 needs GDS OA for streamout. */
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cmd_buffer->gds_oa_needed = true;
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cmd_buffer->queue_state.gds_oa_needed = true;
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}
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}
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@ -8773,7 +8762,7 @@ radv_bind_tess_ctrl_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv
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{
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radv_bind_pre_rast_shader(cmd_buffer, tcs);
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cmd_buffer->tess_rings_needed = true;
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cmd_buffer->queue_state.tess_rings_needed = true;
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/* Always re-emit patch control points/domain origin when a new pipeline with tessellation is
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* bound because a bunch of parameters (user SGPRs, TCS vertices out, ccw, etc) can be different.
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@ -8802,8 +8791,8 @@ radv_bind_geometry_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
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radv_bind_pre_rast_shader(cmd_buffer, gs);
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if (!gs->info.is_ngg && !gs->info.merged_shader_compiled_separately) {
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cmd_buffer->esgs_ring_size_needed = MAX2(cmd_buffer->esgs_ring_size_needed, gs->regs.gs.esgs_ring_size);
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cmd_buffer->gsvs_ring_size_needed = MAX2(cmd_buffer->gsvs_ring_size_needed, gs->regs.gs.gsvs_ring_size);
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cmd_buffer->queue_state.esgs_ring_size_needed = MAX2(cmd_buffer->queue_state.esgs_ring_size_needed, gs->regs.gs.esgs_ring_size);
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cmd_buffer->queue_state.gsvs_ring_size_needed = MAX2(cmd_buffer->queue_state.gsvs_ring_size_needed, gs->regs.gs.gsvs_ring_size);
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}
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/* Re-emit the VS prolog when the geometry shader is compiled separately because shader configs
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@ -8836,7 +8825,7 @@ radv_bind_mesh_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shad
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{
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radv_bind_pre_rast_shader(cmd_buffer, ms);
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cmd_buffer->mesh_scratch_ring_needed |= ms->info.ms.needs_ms_scratch_ring;
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cmd_buffer->queue_state.mesh_scratch_ring_needed |= ms->info.ms.needs_ms_scratch_ring;
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}
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static void
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@ -8848,7 +8837,7 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
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const struct radv_shader *previous_ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
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if (ps->info.ps.needs_sample_positions) {
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cmd_buffer->sample_positions_needed = true;
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cmd_buffer->queue_state.sample_positions_needed = true;
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}
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if (ps->info.ps.has_epilog)
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@ -8887,7 +8876,7 @@ radv_bind_task_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_shad
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if (radv_get_user_sgpr_info(ts, AC_UD_TASK_STATE)->sgpr_idx != -1)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_TASK_STATE;
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cmd_buffer->task_rings_needed = true;
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cmd_buffer->queue_state.task_rings_needed = true;
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}
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static void
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@ -8899,7 +8888,7 @@ radv_bind_rt_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *rt_p
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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const unsigned max_scratch_waves = radv_get_max_scratch_waves(device, rt_prolog);
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cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted, max_scratch_waves);
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cmd_buffer->queue_state.compute_scratch_waves_wanted = MAX2(cmd_buffer->queue_state.compute_scratch_waves_wanted, max_scratch_waves);
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cmd_buffer->shader_upload_seq = MAX2(cmd_buffer->shader_upload_seq, rt_prolog->upload_seq);
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@ -8992,11 +8981,11 @@ radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader,
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radv_bind_task_shader(cmd_buffer, shader);
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break;
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case MESA_SHADER_COMPUTE: {
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cmd_buffer->compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave);
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cmd_buffer->queue_state.compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->queue_state.compute_scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave);
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const unsigned max_stage_waves = radv_get_max_scratch_waves(device, shader);
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cmd_buffer->compute_scratch_waves_wanted = MAX2(cmd_buffer->compute_scratch_waves_wanted, max_stage_waves);
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cmd_buffer->queue_state.compute_scratch_waves_wanted = MAX2(cmd_buffer->queue_state.compute_scratch_waves_wanted, max_stage_waves);
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break;
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}
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case MESA_SHADER_INTERSECTION:
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@ -9010,11 +8999,11 @@ radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader,
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cmd_buffer->state.active_stages |= mesa_to_vk_shader_stage(stage);
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if (mesa_to_vk_shader_stage(stage) & RADV_GRAPHICS_STAGE_BITS) {
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cmd_buffer->scratch_size_per_wave_needed =
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MAX2(cmd_buffer->scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave);
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cmd_buffer->queue_state.scratch_size_per_wave_needed =
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MAX2(cmd_buffer->queue_state.scratch_size_per_wave_needed, shader->config.scratch_bytes_per_wave);
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const unsigned max_stage_waves = radv_get_max_scratch_waves(device, shader);
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cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, max_stage_waves);
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cmd_buffer->queue_state.scratch_waves_wanted = MAX2(cmd_buffer->queue_state.scratch_waves_wanted, max_stage_waves);
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}
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cmd_buffer->shader_upload_seq = MAX2(cmd_buffer->shader_upload_seq, shader->upload_seq);
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@ -9896,6 +9885,25 @@ radv_handle_depth_fbfetch_output(struct radv_cmd_buffer *cmd_buffer, struct radv
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att->iview->image, &range);
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}
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static void
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radv_merge_queue_state(const struct radv_cmd_buffer_queue_state *src, struct radv_cmd_buffer_queue_state *dst)
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{
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dst->scratch_size_per_wave_needed = MAX2(dst->scratch_size_per_wave_needed, src->scratch_size_per_wave_needed);
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dst->scratch_waves_wanted = MAX2(dst->scratch_waves_wanted, src->scratch_waves_wanted);
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dst->compute_scratch_size_per_wave_needed =
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MAX2(dst->compute_scratch_size_per_wave_needed, src->compute_scratch_size_per_wave_needed);
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dst->compute_scratch_waves_wanted = MAX2(dst->compute_scratch_waves_wanted, src->compute_scratch_waves_wanted);
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dst->esgs_ring_size_needed = MAX2(dst->esgs_ring_size_needed, src->esgs_ring_size_needed);
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dst->gsvs_ring_size_needed = MAX2(dst->gsvs_ring_size_needed, src->gsvs_ring_size_needed);
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dst->tess_rings_needed |= src->tess_rings_needed;
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dst->task_rings_needed |= src->task_rings_needed;
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dst->mesh_scratch_ring_needed |= src->mesh_scratch_ring_needed;
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dst->gds_needed |= src->gds_needed;
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dst->gds_oa_needed |= src->gds_oa_needed;
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dst->sample_positions_needed |= src->sample_positions_needed;
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}
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VKAPI_ATTR void VKAPI_CALL
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radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer *pCmdBuffers)
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{
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@ -9924,30 +9932,7 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
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*/
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const bool allow_ib2 = !secondary->state.uses_draw_indirect || pdev->info.gfx_level >= GFX8;
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primary->scratch_size_per_wave_needed =
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MAX2(primary->scratch_size_per_wave_needed, secondary->scratch_size_per_wave_needed);
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primary->scratch_waves_wanted = MAX2(primary->scratch_waves_wanted, secondary->scratch_waves_wanted);
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primary->compute_scratch_size_per_wave_needed =
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MAX2(primary->compute_scratch_size_per_wave_needed, secondary->compute_scratch_size_per_wave_needed);
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primary->compute_scratch_waves_wanted =
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MAX2(primary->compute_scratch_waves_wanted, secondary->compute_scratch_waves_wanted);
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if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
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primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
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if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
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primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
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if (secondary->tess_rings_needed)
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primary->tess_rings_needed = true;
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if (secondary->task_rings_needed)
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primary->task_rings_needed = true;
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if (secondary->mesh_scratch_ring_needed)
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primary->mesh_scratch_ring_needed = true;
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if (secondary->sample_positions_needed)
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primary->sample_positions_needed = true;
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if (secondary->gds_needed)
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primary->gds_needed = true;
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if (secondary->gds_oa_needed)
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primary->gds_oa_needed = true;
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radv_merge_queue_state(&secondary->queue_state, &primary->queue_state);
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primary->shader_upload_seq = MAX2(primary->shader_upload_seq, secondary->shader_upload_seq);
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@ -13110,8 +13095,8 @@ radv_bind_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
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radv_get_legacy_gs_info(&device->compiler_info, &es->info, &gs->info);
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radv_precompute_registers_hw_gs(device, &es->info, gs);
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cmd_buffer->esgs_ring_size_needed = MAX2(cmd_buffer->esgs_ring_size_needed, gs->regs.gs.esgs_ring_size);
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cmd_buffer->gsvs_ring_size_needed = MAX2(cmd_buffer->gsvs_ring_size_needed, gs->regs.gs.gsvs_ring_size);
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cmd_buffer->queue_state.esgs_ring_size_needed = MAX2(cmd_buffer->queue_state.esgs_ring_size_needed, gs->regs.gs.esgs_ring_size);
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cmd_buffer->queue_state.gsvs_ring_size_needed = MAX2(cmd_buffer->queue_state.gsvs_ring_size_needed, gs->regs.gs.gsvs_ring_size);
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}
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}
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@ -13805,10 +13790,10 @@ radv_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, VkBool32 isPr
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if (ies) {
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radv_cs_add_buffer(device->ws, cs->b, ies->bo);
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cmd_buffer->compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, ies->compute_scratch_size_per_wave);
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cmd_buffer->compute_scratch_waves_wanted =
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MAX2(cmd_buffer->compute_scratch_waves_wanted, ies->compute_scratch_waves);
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cmd_buffer->queue_state.compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->queue_state.compute_scratch_size_per_wave_needed, ies->compute_scratch_size_per_wave);
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cmd_buffer->queue_state.compute_scratch_waves_wanted =
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MAX2(cmd_buffer->queue_state.compute_scratch_waves_wanted, ies->compute_scratch_waves);
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}
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/* Secondary command buffers are banned. */
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@ -14236,8 +14221,8 @@ radv_emit_rt_stack_size(struct radv_cmd_buffer *cmd_buffer)
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uint32_t scratch_bytes_per_wave =
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align(cmd_buffer->state.rt_stack_size * wave_size, pdev->info.scratch_wavesize_granularity);
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cmd_buffer->compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, scratch_bytes_per_wave);
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cmd_buffer->queue_state.compute_scratch_size_per_wave_needed =
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MAX2(cmd_buffer->queue_state.compute_scratch_size_per_wave_needed, scratch_bytes_per_wave);
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if (cmd_buffer->state.rt_stack_size)
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rsrc2 |= S_00B12C_SCRATCH_EN(1);
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@ -511,6 +511,21 @@ struct radv_cmd_stream {
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struct ac_buffered_sh_regs buffered_sh_regs;
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};
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struct radv_cmd_buffer_queue_state {
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uint32_t scratch_size_per_wave_needed;
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uint32_t scratch_waves_wanted;
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uint32_t compute_scratch_size_per_wave_needed;
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uint32_t compute_scratch_waves_wanted;
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uint32_t esgs_ring_size_needed;
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uint32_t gsvs_ring_size_needed;
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bool tess_rings_needed;
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bool task_rings_needed;
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bool mesh_scratch_ring_needed;
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bool gds_needed; /* Emulated queries on GFX10-GFX10.3 */
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bool gds_oa_needed; /* NGG streamout on GFX11-GFX11.5 */
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bool sample_positions_needed;
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};
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struct radv_cmd_buffer {
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struct vk_command_buffer vk;
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@ -533,18 +548,7 @@ struct radv_cmd_buffer {
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struct radv_cmd_buffer_upload upload;
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uint32_t scratch_size_per_wave_needed;
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uint32_t scratch_waves_wanted;
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uint32_t compute_scratch_size_per_wave_needed;
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uint32_t compute_scratch_waves_wanted;
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uint32_t esgs_ring_size_needed;
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uint32_t gsvs_ring_size_needed;
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bool tess_rings_needed;
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bool task_rings_needed;
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bool mesh_scratch_ring_needed;
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bool gds_needed; /* Emulated queries on GFX10-GFX10.3 */
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bool gds_oa_needed; /* NGG streamout on GFX11-GFX11.5 */
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bool sample_positions_needed;
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struct radv_cmd_buffer_queue_state queue_state;
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uint64_t gfx9_fence_va;
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uint32_t gfx9_fence_idx;
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@ -648,7 +648,7 @@ radv_begin_pipeline_stat_query(struct radv_cmd_buffer *cmd_buffer, struct radv_q
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}
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/* Record that the command buffer needs GDS. */
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cmd_buffer->gds_needed = true;
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cmd_buffer->queue_state.gds_needed = true;
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if (!cmd_buffer->state.active_emulated_pipeline_queries)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
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@ -674,7 +674,7 @@ radv_begin_pipeline_stat_query(struct radv_cmd_buffer *cmd_buffer, struct radv_q
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ac_emit_cp_write_data_imm(ace_cs->b, V_371_MICRO_ENGINE, va + task_invoc_offset + 4, 0x80000000);
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/* Record that the command buffer needs GDS. */
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cmd_buffer->gds_needed = true;
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cmd_buffer->queue_state.gds_needed = true;
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if (!cmd_buffer->state.active_pipeline_ace_queries)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
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@ -1366,7 +1366,7 @@ radv_begin_pg_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *
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ac_emit_cp_write_data_imm(cs->b, V_371_MICRO_ENGINE, va + 36, 0x80000000);
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/* Record that the command buffer needs GDS. */
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cmd_buffer->gds_needed = true;
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cmd_buffer->queue_state.gds_needed = true;
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if (!cmd_buffer->state.active_emulated_prims_gen_queries)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
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@ -1593,7 +1593,7 @@ radv_begin_ms_prim_query(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
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ac_emit_cp_write_data_imm(cs->b, V_371_MICRO_ENGINE, va + 4, 0x80000000);
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/* Record that the command buffer needs GDS. */
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cmd_buffer->gds_needed = true;
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cmd_buffer->queue_state.gds_needed = true;
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if (!cmd_buffer->state.active_emulated_prims_gen_queries)
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_SHADER_QUERY;
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@ -1228,19 +1228,19 @@ radv_update_preambles(struct radv_queue_state *queue, struct radv_device *device
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for (uint32_t j = 0; j < cmd_buffer_count; j++) {
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struct radv_cmd_buffer *cmd_buffer = container_of(cmd_buffers[j], struct radv_cmd_buffer, vk);
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needs.scratch_size_per_wave = MAX2(needs.scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
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needs.scratch_waves = MAX2(needs.scratch_waves, cmd_buffer->scratch_waves_wanted);
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||||
needs.scratch_size_per_wave = MAX2(needs.scratch_size_per_wave, cmd_buffer->queue_state.scratch_size_per_wave_needed);
|
||||
needs.scratch_waves = MAX2(needs.scratch_waves, cmd_buffer->queue_state.scratch_waves_wanted);
|
||||
needs.compute_scratch_size_per_wave =
|
||||
MAX2(needs.compute_scratch_size_per_wave, cmd_buffer->compute_scratch_size_per_wave_needed);
|
||||
needs.compute_scratch_waves = MAX2(needs.compute_scratch_waves, cmd_buffer->compute_scratch_waves_wanted);
|
||||
needs.esgs_ring_size = MAX2(needs.esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
|
||||
needs.gsvs_ring_size = MAX2(needs.gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
|
||||
needs.tess_rings |= cmd_buffer->tess_rings_needed;
|
||||
needs.task_rings |= cmd_buffer->task_rings_needed;
|
||||
needs.mesh_scratch_ring |= cmd_buffer->mesh_scratch_ring_needed;
|
||||
needs.gds |= cmd_buffer->gds_needed;
|
||||
needs.gds_oa |= cmd_buffer->gds_oa_needed;
|
||||
needs.sample_positions |= cmd_buffer->sample_positions_needed;
|
||||
MAX2(needs.compute_scratch_size_per_wave, cmd_buffer->queue_state.compute_scratch_size_per_wave_needed);
|
||||
needs.compute_scratch_waves = MAX2(needs.compute_scratch_waves, cmd_buffer->queue_state.compute_scratch_waves_wanted);
|
||||
needs.esgs_ring_size = MAX2(needs.esgs_ring_size, cmd_buffer->queue_state.esgs_ring_size_needed);
|
||||
needs.gsvs_ring_size = MAX2(needs.gsvs_ring_size, cmd_buffer->queue_state.gsvs_ring_size_needed);
|
||||
needs.tess_rings |= cmd_buffer->queue_state.tess_rings_needed;
|
||||
needs.task_rings |= cmd_buffer->queue_state.task_rings_needed;
|
||||
needs.mesh_scratch_ring |= cmd_buffer->queue_state.mesh_scratch_ring_needed;
|
||||
needs.gds |= cmd_buffer->queue_state.gds_needed;
|
||||
needs.gds_oa |= cmd_buffer->queue_state.gds_oa_needed;
|
||||
needs.sample_positions |= cmd_buffer->queue_state.sample_positions_needed;
|
||||
*use_perf_counters |= cmd_buffer->state.uses_perf_counters;
|
||||
*has_follower |= !!cmd_buffer->gang.cs;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue