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radeonsi: replace SI_RESOURCE_FLAG_UNMAPPABLE with PIPE_RESOURCE_FLAG_UNMAPPABLE

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
This commit is contained in:
Marek Olšák 2022-01-22 11:25:27 -05:00 • committed by Marge Bot
parent 790362c10e
commit f865631b1b
10 changed files with 13 additions and 13 deletions
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4
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -104,7 +104,7 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
res->b.b.flags & PIPE_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC;
}
@ -589,7 +589,7 @@ static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
templ->width0 <= sscreen->options.tc_max_cpu_storage_size);
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
buf->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
buf->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
si_init_resource_fields(sscreen, buf, templ->width0, alignment);

2
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -116,7 +116,7 @@ static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture
return false;
tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
si_aligned_buffer_create(&sscreen->b, PIPE_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
tex->surface.cmask_size, 1 << tex->surface.cmask_alignment_log2);
if (tex->cmask_buffer == NULL)
return false;

2
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -463,7 +463,7 @@ static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_s
sctx->compute_scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
scratch_needed, sctx->screen->info.pte_fragment_size);

2
src/gallium/drivers/radeonsi/si_cp_dma.c
View file

@ -259,7 +259,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, uns
if (!sctx->scratch_buffer || sctx->scratch_buffer->b.b.width0 < scratch_size) {
si_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = si_aligned_buffer_create(&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT, scratch_size, 256);
if (!sctx->scratch_buffer)
return;

2
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -153,7 +153,7 @@ void si_init_cp_reg_shadowing(struct si_context *sctx)
sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
sctx->shadowed_regs =
si_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
SI_SHADOWED_REG_BUFFER_SIZE,
4096);

2
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -604,7 +604,7 @@ static struct si_resource* si_get_wait_mem_scratch_bo(struct si_context *ctx, bo
if (!ctx->wait_mem_scratch_tmz)
ctx->wait_mem_scratch_tmz =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE |
PIPE_RESOURCE_FLAG_UNMAPPABLE |
SI_RESOURCE_FLAG_DRIVER_INTERNAL |
PIPE_RESOURCE_FLAG_ENCRYPTED,
PIPE_USAGE_DEFAULT, 8,

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -649,7 +649,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
if (sctx->chip_class >= GFX9) {
sctx->wait_mem_scratch =
si_aligned_buffer_create(screen,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT, 8,
sscreen->info.tcc_cache_line_size);
if (!sctx->wait_mem_scratch)

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -133,7 +133,7 @@ extern "C" {
#define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
#define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
#define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
/* gap */
#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)

6
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -3835,7 +3835,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
esgs_ring_size, sctx->screen->info.pte_fragment_size);
if (!sctx->esgs_ring)
@ -3846,7 +3846,7 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
pipe_aligned_buffer_create(sctx->b.screen,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, sctx->screen->info.pte_fragment_size);
if (!sctx->gsvs_ring)
@ -4079,7 +4079,7 @@ bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
sctx->scratch_buffer = si_aligned_buffer_create(
&sctx->screen->b,
SI_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT, scratch_needed_size,
sctx->screen->info.pte_fragment_size);
if (!sctx->scratch_buffer)

2
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1014,7 +1014,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
resource->gpu_address = plane0->buffer.gpu_address;
} else if (!(surface->flags & RADEON_SURF_IMPORTED)) {
if (base->flags & PIPE_RESOURCE_FLAG_SPARSE)
resource->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
resource->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
if (base->bind & PIPE_BIND_PRIME_BLIT_DST)
resource->b.b.flags |= SI_RESOURCE_FLAG_UNCACHED;