fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 07:28:11 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv,iris: Use WriteImmediate instead of Z flush for WA

Browse source 
According to the HSD, this is an alternative option for Wa_14016712196.
Taking this option allows us to combine this workaround with a couple
other depth workarounds. Make sure to execute these workarounds before
the workaround for the depth register mode, so that the stalling flush
is not impacted.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29922>
This commit is contained in:
Nanley Chery 2024-07-03 00:02:49 -04:00 • committed by Marge Bot
parent db6ae41c65
commit f854161928
2 changed files with 22 additions and 35 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/gallium/drivers/iris/iris_state.c
View file

@ -7813,19 +7813,9 @@ iris_upload_dirty_render_state(struct iris_context *ice,
iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));
/* Wa_14016712196:
* Emit depth flush after state that sends implicit depth flush.
*/
if (intel_needs_workaround(batch->screen->devinfo, 14016712196)) {
iris_emit_pipe_control_flush(batch, "Wa_14016712196",
PIPE_CONTROL_DEPTH_CACHE_FLUSH);
}
if (zres)
genX(emit_depth_state_workarounds)(ice, batch, &zres->surf);
if (intel_needs_workaround(batch->screen->devinfo, 1408224581) ||
intel_needs_workaround(batch->screen->devinfo, 14014097488)) {
intel_needs_workaround(batch->screen->devinfo, 14014097488) ||
intel_needs_workaround(batch->screen->devinfo, 14016712196)) {
/* Wa_1408224581
*
* Workaround: Gfx12LP Astep only An additional pipe control with
@ -7833,13 +7823,17 @@ iris_upload_dirty_render_state(struct iris_context *ice,
* have an additional pipe control after the stencil state whenever
* the surface state bits of this state is changing).
*
* This also seems sufficient to handle Wa_14014097488.
* This also seems sufficient to handle Wa_14014097488 and
* Wa_14016712196.
*/
iris_emit_pipe_control_write(batch, "WA for stencil state",
iris_emit_pipe_control_write(batch, "WA for depth/stencil state",
PIPE_CONTROL_WRITE_IMMEDIATE,
screen->workaround_address.bo,
screen->workaround_address.offset, 0);
}
if (zres)
genX(emit_depth_state_workarounds)(ice, batch, &zres->surf);
}
if (dirty & (IRIS_DIRTY_DEPTH_BUFFER | IRIS_DIRTY_WM_DEPTH_STENCIL)) {

35
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4723,21 +4723,9 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info);
/* Wa_14016712196:
* Emit depth flush after state that sends implicit depth flush.
*/
if (intel_needs_workaround(cmd_buffer->device->info, 14016712196)) {
genx_batch_emit_pipe_control(&cmd_buffer->batch,
cmd_buffer->device->info,
cmd_buffer->state.current_pipeline,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT);
}
if (info.depth_surf)
genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, info.depth_surf);
if (intel_needs_workaround(cmd_buffer->device->info, 1408224581) ||
intel_needs_workaround(cmd_buffer->device->info, 14014097488)) {
intel_needs_workaround(cmd_buffer->device->info, 14014097488) ||
intel_needs_workaround(cmd_buffer->device->info, 14016712196)) {
/* Wa_1408224581
*
* Workaround: Gfx12LP Astep only An additional pipe control with
@ -4745,7 +4733,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
* an additional pipe control after the stencil state whenever the
* surface state bits of this state is changing).
*
* This also seems sufficient to handle Wa_14014097488.
* This also seems sufficient to handle Wa_14014097488 and
* Wa_14016712196.
*/
genx_batch_emit_pipe_control_write(&cmd_buffer->batch, device->info,
cmd_buffer->state.current_pipeline,
@ -4753,6 +4742,9 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
device->workaround_address, 0, 0);
}
if (info.depth_surf)
genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, info.depth_surf);
cmd_buffer->state.hiz_enabled = isl_aux_usage_has_hiz(info.hiz_usage);
}
@ -4792,14 +4784,15 @@ cmd_buffer_emit_cps_control_buffer(struct anv_cmd_buffer *cmd_buffer,
isl_emit_cpb_control_s(&device->isl_dev, dw, &info);
/* Wa_14016712196:
* Emit depth flush after state that sends implicit depth flush.
* Emit dummy pipe control after state that sends implicit depth flush.
*/
if (intel_needs_workaround(cmd_buffer->device->info, 14016712196)) {
genx_batch_emit_pipe_control(&cmd_buffer->batch,
cmd_buffer->device->info,
cmd_buffer->state.current_pipeline,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT);
if (intel_needs_workaround(device->info, 14016712196)) {
genx_batch_emit_pipe_control_write(&cmd_buffer->batch, device->info,
cmd_buffer->state.current_pipeline,
WriteImmediateData,
device->workaround_address, 0, 0);
}
#endif /* GFX_VERx10 >= 125 */
}