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https://gitlab.freedesktop.org/mesa/mesa.git
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nak: Use nak_nir_lower_vtg_io
This massively simplifies nak_from_nir.rs because it lets us do all the annoying NIR fiddling in NIR and not in the back-end. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
7ece220f96
commit
f85069ed57
4 changed files with 184 additions and 201 deletions
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@ -1478,6 +1478,18 @@ impl SM75Instr {
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}
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}
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fn encode_al2p(&mut self, op: &OpAL2P) {
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self.set_opcode(0x920);
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self.set_dst(op.dst);
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self.set_reg_src(24..32, op.offset);
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self.set_field(40..50, op.access.addr);
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self.set_field(74..76, 0_u8); // comps
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assert!(!op.access.patch);
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self.set_bit(79, op.access.output);
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}
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fn encode_ald(&mut self, op: &OpALd) {
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self.set_opcode(0x321);
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@ -1774,6 +1786,7 @@ impl SM75Instr {
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Op::St(op) => si.encode_st(&op),
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Op::Atom(op) => si.encode_atom(&op),
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Op::AtomCas(op) => si.encode_atom_cas(&op),
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Op::AL2P(op) => si.encode_al2p(&op),
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Op::ALd(op) => si.encode_ald(&op),
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Op::ASt(op) => si.encode_ast(&op),
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Op::Ipa(op) => si.encode_ipa(&op),
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@ -1200,6 +1200,105 @@ impl<'a> ShaderFromNir<'a> {
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) {
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let srcs = intrin.srcs_as_slice();
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match intrin.intrinsic {
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nir_intrinsic_al2p_nv => {
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let offset = self.get_src(&srcs[0]);
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let addr = u16::try_from(intrin.base()).unwrap();
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let flags = intrin.flags();
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let flags: nak_nir_attr_io_flags =
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unsafe { std::mem::transmute_copy(&flags) };
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let access = AttrAccess {
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addr: addr,
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comps: 1,
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patch: flags.patch(),
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output: flags.output(),
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flags: 0,
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};
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpAL2P {
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dst: dst.into(),
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offset: offset,
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access: access,
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});
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_ald_nv | nir_intrinsic_ast_nv => {
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let addr = u16::try_from(intrin.base()).unwrap();
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let base = u16::try_from(intrin.range_base()).unwrap();
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let range = u16::try_from(intrin.range()).unwrap();
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let range = base..(base + range);
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let flags = intrin.flags();
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let flags: nak_nir_attr_io_flags =
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unsafe { std::mem::transmute_copy(&flags) };
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assert!(!flags.patch() || !flags.phys());
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if let ShaderIoInfo::Vtg(io) = &mut self.info.io {
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if flags.patch() {
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match &mut self.info.stage {
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ShaderStageInfo::TessellationInit(stage) => {
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assert!(flags.output());
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stage.per_patch_attribute_count = max(
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stage.per_patch_attribute_count,
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(range.end / 4).try_into().unwrap(),
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);
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}
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ShaderStageInfo::Tessellation => (),
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_ => panic!("Patch I/O not supported"),
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}
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} else {
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if flags.output() {
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if intrin.intrinsic == nir_intrinsic_ast_nv {
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io.mark_store_req(range.clone());
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}
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io.mark_attrs_written(range);
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} else {
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io.mark_attrs_read(range);
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}
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}
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} else {
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panic!("Must be a VTG stage");
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}
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let access = AttrAccess {
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addr: addr,
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comps: intrin.num_components,
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patch: flags.patch(),
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output: flags.output(),
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flags: flags.phys().into(),
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};
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if intrin.intrinsic == nir_intrinsic_ald_nv {
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let vtx = self.get_src(&srcs[0]);
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let offset = self.get_src(&srcs[1]);
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assert!(intrin.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, access.comps);
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b.push_op(OpALd {
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dst: dst.into(),
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vtx: vtx,
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offset: offset,
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access: access,
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});
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self.set_dst(&intrin.def, dst);
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} else if intrin.intrinsic == nir_intrinsic_ast_nv {
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assert!(srcs[0].bit_size() == 32);
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let data = self.get_src(&srcs[0]);
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let vtx = self.get_src(&srcs[1]);
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let offset = self.get_src(&srcs[2]);
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b.push_op(OpASt {
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data: data,
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vtx: vtx,
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offset: offset,
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access: access,
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});
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} else {
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panic!("Invalid VTG I/O intrinsic");
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}
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}
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nir_intrinsic_bindless_image_atomic => {
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let handle = self.get_src(&srcs[0]);
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let dim = self.get_image_dim(intrin);
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@ -1366,173 +1465,33 @@ impl<'a> ShaderFromNir<'a> {
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});
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_load_input
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| nir_intrinsic_load_output
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| nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output
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| nir_intrinsic_store_output
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| nir_intrinsic_store_per_vertex_output => {
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let comps = intrin.num_components;
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let store_data = match intrin.intrinsic {
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nir_intrinsic_load_input
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| nir_intrinsic_load_output
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| nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output => {
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assert!(intrin.def.bit_size() == 32);
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assert!(intrin.def.num_components() == comps);
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None
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}
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nir_intrinsic_store_output
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| nir_intrinsic_store_per_vertex_output => {
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assert!(srcs[0].bit_size() == 32);
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assert!(srcs[0].num_components() == comps);
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Some(self.get_src(&srcs[0]))
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}
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_ => panic!("Unhandled intrinsic"),
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nir_intrinsic_load_input => {
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let ShaderIoInfo::Fragment(io) = &mut self.info.io else {
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panic!("load_input is only used for fragment shaders");
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};
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let (vtx, offset, offset_as_u32) = match intrin.intrinsic {
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nir_intrinsic_load_input | nir_intrinsic_load_output => (
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Src::new_zero(),
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self.get_src(&srcs[0]),
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srcs[0].as_uint(),
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),
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nir_intrinsic_load_per_vertex_input
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| nir_intrinsic_load_per_vertex_output => (
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self.get_src(&srcs[0]),
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self.get_src(&srcs[1]),
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srcs[1].as_uint(),
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),
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nir_intrinsic_store_output => (
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Src::new_zero(),
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self.get_src(&srcs[1]),
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srcs[1].as_uint(),
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),
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nir_intrinsic_store_per_vertex_output => (
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self.get_src(&srcs[1]),
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self.get_src(&srcs[2]),
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srcs[2].as_uint(),
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),
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_ => panic!("Unhandled intrinsic"),
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};
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assert!(intrin.def.bit_size() == 32);
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let comps = intrin.def.num_components;
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let base = u16::try_from(intrin.base()).unwrap();
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let range = u16::try_from(intrin.range()).unwrap();
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let comp = u16::try_from(intrin.component()).unwrap();
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let addr = u16::try_from(intrin.base()).unwrap()
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+ u16::try_from(srcs[0].as_uint().unwrap()).unwrap()
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+ 4 * u16::try_from(intrin.component()).unwrap();
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let (range, addr, offset) = match offset_as_u32 {
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Some(imm) => {
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let imm = u16::try_from(imm).unwrap();
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let addr = base + imm + 4 * comp;
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let range = addr..(addr + 4 * u16::from(comps));
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(range, addr, Src::new_zero())
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}
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None => {
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let range = base..(base + range);
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(range, base + 4 * comp, offset)
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}
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};
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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for c in 0..comps {
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let c_addr = addr + 4 * u16::from(c);
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let stage = self.nir.info.stage();
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let (output, patch) = match intrin.intrinsic {
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nir_intrinsic_load_input => {
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(false, stage == MESA_SHADER_TESS_EVAL)
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}
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nir_intrinsic_load_output | nir_intrinsic_store_output => {
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(true, stage == MESA_SHADER_TESS_CTRL)
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}
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nir_intrinsic_load_per_vertex_input => (false, false),
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nir_intrinsic_load_per_vertex_output
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| nir_intrinsic_store_per_vertex_output => (true, false),
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_ => panic!("Unhandled intrinsic"),
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};
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io.mark_attr_read(c_addr, PixelImap::Constant);
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match &mut self.info.io {
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ShaderIoInfo::None => {
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panic!("Stage does not support load_input")
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}
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ShaderIoInfo::Fragment(io) => {
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if let Some(data) = store_data {
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// We assume these only ever happen in the
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// last block. This is ensured by
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// nir_lower_io_to_temporaries()
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assert!(offset_as_u32 == Some(0));
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assert!(addr % 4 == 0);
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let data = data.as_ssa().unwrap();
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for c in 0..usize::from(comps) {
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let idx =
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usize::from(addr / 4) + usize::from(c);
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self.fs_out_regs[idx] = data[c];
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}
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} else {
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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for c in 0..comps {
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let c_addr = addr + 4 * u16::from(c);
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io.mark_attr_read(c_addr, PixelImap::Constant);
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: c_addr,
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freq: InterpFreq::Constant,
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loc: InterpLoc::Default,
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offset: SrcRef::Zero.into(),
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});
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}
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self.set_dst(&intrin.def, dst);
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}
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}
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ShaderIoInfo::Vtg(io) => {
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if patch {
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match &mut self.info.stage {
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ShaderStageInfo::TessellationInit(stage) => {
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stage.per_patch_attribute_count = max(
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stage.per_patch_attribute_count,
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(range.end / 4).try_into().unwrap(),
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);
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}
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ShaderStageInfo::Tessellation => (),
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_ => panic!("Patch I/O not supported"),
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}
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} else {
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if output {
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if store_data.is_none() {
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io.mark_store_req(range.clone());
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}
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io.mark_attrs_written(range);
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} else {
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io.mark_attrs_read(range);
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}
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}
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let access = AttrAccess {
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addr: addr,
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comps: comps,
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patch: patch,
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output: output,
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flags: 0,
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};
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if let Some(data) = store_data {
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b.push_op(OpASt {
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vtx: vtx,
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offset: offset,
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data: data,
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access: access,
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});
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} else {
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let dst = b.alloc_ssa(RegFile::GPR, comps);
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b.push_op(OpALd {
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dst: dst.into(),
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vtx: vtx,
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offset: offset,
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access: access,
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});
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self.set_dst(&intrin.def, dst);
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}
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}
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b.push_op(OpIpa {
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dst: dst[usize::from(c)].into(),
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addr: c_addr,
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freq: InterpFreq::Constant,
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loc: InterpLoc::Default,
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offset: SrcRef::Zero.into(),
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});
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}
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self.set_dst(&intrin.def, dst);
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}
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nir_intrinsic_load_interpolated_input => {
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let bary =
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@ -1851,6 +1810,22 @@ impl<'a> ShaderFromNir<'a> {
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access: access,
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});
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}
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nir_intrinsic_store_output => {
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let ShaderIoInfo::Fragment(io) = &mut self.info.io else {
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panic!("load_input is only used for fragment shaders");
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};
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let data = self.get_src(&srcs[0]);
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let addr = u16::try_from(intrin.base()).unwrap()
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+ u16::try_from(srcs[1].as_uint().unwrap()).unwrap()
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+ 4 * u16::try_from(intrin.component()).unwrap();
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assert!(addr % 4 == 0);
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for c in 0..usize::from(intrin.num_components) {
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let idx = usize::from(addr / 4) + usize::from(c);
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self.fs_out_regs[idx] = data.as_ssa().unwrap()[c];
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}
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}
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nir_intrinsic_store_scratch => {
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let data = self.get_src(&srcs[0]);
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let size_B =
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@ -3313,6 +3313,34 @@ impl fmt::Display for OpAtomCas {
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}
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}
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpAL2P {
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pub dst: Dst,
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#[src_type(GPR)]
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pub offset: Src,
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pub access: AttrAccess,
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}
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impl fmt::Display for OpAL2P {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(f, "AL2P")?;
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if self.access.output {
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write!(f, ".O")?;
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}
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if self.access.patch {
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write!(f, ".P")?;
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}
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write!(f, " {} a[{:#x}", self.dst, self.access.addr)?;
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if !self.offset.is_zero() {
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write!(f, "+{}", self.offset)?;
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}
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write!(f, "]")
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}
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}
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpALd {
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@ -4019,6 +4047,7 @@ pub enum Op {
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St(OpSt),
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Atom(OpAtom),
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AtomCas(OpAtomCas),
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AL2P(OpAL2P),
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ALd(OpALd),
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ASt(OpASt),
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Ipa(OpIpa),
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@ -4446,6 +4475,7 @@ impl Instr {
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| Op::St(_)
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| Op::Atom(_)
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| Op::AtomCas(_)
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| Op::AL2P(_)
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| Op::ALd(_)
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| Op::ASt(_)
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| Op::Ipa(_)
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@ -304,18 +304,6 @@ nak_sysval_sysval_idx(gl_system_value sysval)
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}
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}
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static nir_def *
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nak_nir_isberd(nir_builder *b, nir_def *vertex)
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{
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nir_def *info = nir_load_sysval_nv(b, 32, .base = NAK_SV_INVOCATION_INFO,
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.access = ACCESS_CAN_REORDER);
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nir_def *lo = nir_extract_u8_imm(b, info, 0);
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nir_def *hi = nir_extract_u8_imm(b, info, 2);
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nir_def *idx = nir_iadd(b, nir_imul(b, lo, hi), vertex);
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return nir_isberd_nv(b, idx);
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}
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static bool
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nak_nir_lower_system_value_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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@ -338,8 +326,8 @@ nak_nir_lower_system_value_instr(nir_builder *b, nir_instr *instr, void *data)
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case nir_intrinsic_load_primitive_id: {
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assert(b->shader->info.stage == MESA_SHADER_TESS_CTRL ||
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b->shader->info.stage == MESA_SHADER_TESS_EVAL);
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nir_def *idx = nak_nir_isberd(b, nir_imm_int(b, 0));
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val = nir_load_per_vertex_input(b, 1, 32, idx, nir_imm_int(b, 0),
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val = nir_load_per_vertex_input(b, 1, 32, nir_imm_int(b, 0),
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nir_imm_int(b, 0),
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.base = NAK_ATTR_PRIMITIVE_ID,
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.dest_type = nir_type_int32);
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break;
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@ -423,23 +411,6 @@ nak_nir_lower_system_values(nir_shader *nir)
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NULL);
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}
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static bool
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lower_per_vertex_io_intrin(nir_builder *b,
|
||||
nir_intrinsic_instr *intrin,
|
||||
void *data)
|
||||
{
|
||||
if (intrin->intrinsic != nir_intrinsic_load_per_vertex_input)
|
||||
return false;
|
||||
|
||||
b->cursor = nir_before_instr(&intrin->instr);
|
||||
|
||||
nir_src *vertex = &intrin->src[0];
|
||||
nir_def *idx = nak_nir_isberd(b, vertex->ssa);
|
||||
nir_src_rewrite(vertex, idx);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
nak_nir_lower_varyings(nir_shader *nir, nir_variable_mode modes)
|
||||
{
|
||||
|
|
@ -452,16 +423,6 @@ nak_nir_lower_varyings(nir_shader *nir, nir_variable_mode modes)
|
|||
|
||||
OPT(nir, nir_lower_io, modes, type_size_vec4_bytes, 0);
|
||||
|
||||
switch (nir->info.stage) {
|
||||
case MESA_SHADER_TESS_CTRL:
|
||||
case MESA_SHADER_TESS_EVAL:
|
||||
case MESA_SHADER_GEOMETRY:
|
||||
OPT(nir, nir_shader_intrinsics_pass, lower_per_vertex_io_intrin,
|
||||
nir_metadata_block_index | nir_metadata_dominance, NULL);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return progress;
|
||||
}
|
||||
|
||||
|
|
@ -782,12 +743,16 @@ nak_postprocess_nir(nir_shader *nir,
|
|||
case MESA_SHADER_VERTEX:
|
||||
OPT(nir, nak_nir_lower_vs_inputs);
|
||||
OPT(nir, nak_nir_lower_varyings, nir_var_shader_out);
|
||||
OPT(nir, nir_opt_constant_folding);
|
||||
OPT(nir, nak_nir_lower_vtg_io, nak);
|
||||
break;
|
||||
|
||||
case MESA_SHADER_TESS_CTRL:
|
||||
case MESA_SHADER_TESS_EVAL:
|
||||
case MESA_SHADER_GEOMETRY:
|
||||
OPT(nir, nak_nir_lower_varyings, nir_var_shader_in | nir_var_shader_out);
|
||||
OPT(nir, nir_opt_constant_folding);
|
||||
OPT(nir, nak_nir_lower_vtg_io, nak);
|
||||
break;
|
||||
|
||||
case MESA_SHADER_FRAGMENT:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue