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i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.

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Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2013-12-12 00:44:11 -08:00
parent f5dd608db2
commit f7e76e00b6
3 changed files with 10 additions and 23 deletions
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1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1557,6 +1557,7 @@ void brw_emit_query_end(struct brw_context *brw);
/** gen6_queryobj.c */
void gen6_init_queryobj_functions(struct dd_function_table *functions);
void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, int idx);

12
src/mesa/drivers/dri/i965/brw_queryobj.c
View file

@ -63,10 +63,12 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
/**
* Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
*/
static void
write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
void
brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
{
assert(brw->gen < 6);
/* Emit Sandybridge workaround flush: */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_DEPTH_COUNT
@ -431,7 +433,7 @@ brw_emit_query_begin(struct brw_context *brw)
ensure_bo_has_space(ctx, query);
write_depth_count(brw, query->bo, query->last_index * 2);
brw_write_depth_count(brw, query->bo, query->last_index * 2);
brw->query.begin_emitted = true;
}
@ -453,7 +455,7 @@ brw_emit_query_end(struct brw_context *brw)
if (!brw->query.begin_emitted)
return;
write_depth_count(brw, query->bo, query->last_index * 2 + 1);
brw_write_depth_count(brw, query->bo, query->last_index * 2 + 1);
brw->query.begin_emitted = false;
query->last_index++;

20
src/mesa/drivers/dri/i965/gen6_queryobj.c
View file

@ -39,22 +39,6 @@
#include "intel_batchbuffer.h"
#include "intel_reg.h"
/**
* Emit PIPE_CONTROLs to write the PS_DEPTH_COUNT register into a buffer.
*/
static void
write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
{
/* Emit Sandybridge workaround flush: */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_DEPTH_COUNT
| PIPE_CONTROL_DEPTH_STALL,
query_bo, idx * sizeof(uint64_t), 0, 0);
}
/*
* Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
*
@ -252,7 +236,7 @@ gen6_begin_query(struct gl_context *ctx, struct gl_query_object *q)
case GL_ANY_SAMPLES_PASSED:
case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
case GL_SAMPLES_PASSED_ARB:
write_depth_count(brw, query->bo, 0);
brw_write_depth_count(brw, query->bo, 0);
break;
case GL_PRIMITIVES_GENERATED:
@ -291,7 +275,7 @@ gen6_end_query(struct gl_context *ctx, struct gl_query_object *q)
case GL_ANY_SAMPLES_PASSED:
case GL_ANY_SAMPLES_PASSED_CONSERVATIVE:
case GL_SAMPLES_PASSED_ARB:
write_depth_count(brw, query->bo, 1);
brw_write_depth_count(brw, query->bo, 1);
break;
case GL_PRIMITIVES_GENERATED: