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radeong: flush when changing tiling flags of BO referenced by CS

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This commit is contained in:
Marek Olšák 2010-02-12 00:48:44 +01:00
parent f22ddd8e47
commit f7db96cd8f
1 changed files with 13 additions and 2 deletions
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15
src/gallium/winsys/drm/radeon/core/radeon_buffer.c
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@ -217,9 +217,10 @@ static void radeon_buffer_set_tiling(struct radeon_winsys *ws,
boolean microtiled,
boolean macrotiled)
{
struct radeon_winsys_priv *priv = ((struct radeon_winsys *)ws)->priv;
struct radeon_pipe_buffer *radeon_buffer =
(struct radeon_pipe_buffer*)buffer;
uint32_t flags = 0;
uint32_t flags = 0, old_flags, old_pitch;
if (microtiled) {
flags |= RADEON_BO_FLAGS_MICRO_TILE;
@ -228,7 +229,17 @@ static void radeon_buffer_set_tiling(struct radeon_winsys *ws,
flags |= RADEON_BO_FLAGS_MACRO_TILE;
}
radeon_bo_set_tiling(radeon_buffer->bo, flags, pitch);
radeon_bo_get_tiling(radeon_buffer->bo, &old_flags, &old_pitch);
if (flags != old_flags || pitch != old_pitch) {
/* Tiling determines how DRM treats the buffer data.
* We must flush CS when changing it if the buffer is referenced. */
if (radeon_bo_is_referenced_by_cs(radeon_buffer->bo, priv->cs)) {
priv->flush_cb(priv->flush_data);
}
radeon_bo_set_tiling(radeon_buffer->bo, flags, pitch);
}
}
static void radeon_fence_reference(struct pipe_winsys *ws,