fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 11:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: enable query clear/copy using shaders on MTL/ARL

Browse source 
It seems like an L3 setting is different between DG2 & MTL, breaking
the L3 coherency with CS.

We can apply the same tile cache flush as we do on TGL for now until
we figure out how to configure L3 properly to avoid this.

Tested with :

 $ query_clear_with_blorp_threshold=0 query_copy_with_shader_threshold=0 ./deqp-vk -n dEQP-VK.query_pool.*

to force the shader optimizations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27597>
This commit is contained in:
Lionel Landwerlin 2024-02-13 10:39:05 +00:00 • committed by Marge Bot
parent 53df391d27
commit f733215c12
2 changed files with 7 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/intel/vulkan/anv_private.h
View file

@ -3092,10 +3092,11 @@ enum anv_query_bits {
* vkCopyQueryPoolResults(). * vkCopyQueryPoolResults().
*/ */
#define ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo) \ #define ANV_QUERY_RENDER_TARGET_WRITES_PENDING_BITS(devinfo) \
(((devinfo->verx10 >= 120 && \ (((!ANV_DEVINFO_HAS_COHERENT_L3_CS(devinfo) && \
devinfo->verx10 < 125) ? ANV_QUERY_WRITES_TILE_FLUSH : 0) | \ devinfo->ver >= 12) ? \
ANV_QUERY_WRITES_RT_FLUSH | \ ANV_QUERY_WRITES_TILE_FLUSH : 0) | \
ANV_QUERY_WRITES_CS_STALL) ANV_QUERY_WRITES_RT_FLUSH | \
ANV_QUERY_WRITES_CS_STALL)
#define ANV_QUERY_COMPUTE_WRITES_PENDING_BITS \ #define ANV_QUERY_COMPUTE_WRITES_PENDING_BITS \
(ANV_QUERY_WRITES_DATA_FLUSH | \ (ANV_QUERY_WRITES_DATA_FLUSH | \
ANV_QUERY_WRITES_CS_STALL) ANV_QUERY_WRITES_CS_STALL)

8
src/intel/vulkan/genX_query.c
View file

@ -782,10 +782,7 @@ void genX(CmdResetQueryPool)(
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool); ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
struct anv_physical_device *pdevice = cmd_buffer->device->physical; struct anv_physical_device *pdevice = cmd_buffer->device->physical;
/* Temporarily disable on MTL until we understand why some tests hang. if (queryCount >= pdevice->instance->query_clear_with_blorp_threshold) {
*/
if (queryCount >= pdevice->instance->query_clear_with_blorp_threshold &&
!intel_device_info_is_mtl_or_arl(cmd_buffer->device->info)) {
trace_intel_begin_query_clear_blorp(&cmd_buffer->trace); trace_intel_begin_query_clear_blorp(&cmd_buffer->trace);
anv_cmd_buffer_fill_area(cmd_buffer, anv_cmd_buffer_fill_area(cmd_buffer,
@ -1840,8 +1837,7 @@ void genX(CmdCopyQueryPoolResults)(
struct anv_device *device = cmd_buffer->device; struct anv_device *device = cmd_buffer->device;
struct anv_physical_device *pdevice = device->physical; struct anv_physical_device *pdevice = device->physical;
if (queryCount > pdevice->instance->query_copy_with_shader_threshold && if (queryCount > pdevice->instance->query_copy_with_shader_threshold) {
!intel_device_info_is_mtl_or_arl(device->info)) {
copy_query_results_with_shader(cmd_buffer, pool, copy_query_results_with_shader(cmd_buffer, pool,
anv_address_add(buffer->address, anv_address_add(buffer->address,
destOffset), destOffset),