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radeonsi: move rasterizer state into new handling

Browse source 
Signed-off-by: Christian König <deathsimple@vodafone.de>
This commit is contained in:
Christian König 2012-07-17 23:43:00 +02:00
parent 835098a529
commit f67fae0e43
8 changed files with 174 additions and 200 deletions
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14
src/gallium/drivers/radeonsi/evergreen_hw_context.c
View file

@ -57,7 +57,6 @@ static const struct r600_reg si_context_reg_list[] = {
{GROUP_FORCE_NEW_BLOCK, 0},
{R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO},
{GROUP_FORCE_NEW_BLOCK, 0},
{R_02820C_PA_SC_CLIPRECT_RULE, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
{R_028238_CB_TARGET_MASK, 0},
{GROUP_FORCE_NEW_BLOCK, 0},
@ -104,7 +103,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_0286C4_SPI_VS_OUT_CONFIG, 0},
{R_0286CC_SPI_PS_INPUT_ENA, 0},
{R_0286D0_SPI_PS_INPUT_ADDR, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0},
{R_0286D8_SPI_PS_IN_CONTROL, 0},
{R_0286E0_SPI_BARYC_CNTL, 0},
{R_02870C_SPI_SHADER_POS_FORMAT, 0},
@ -120,13 +118,9 @@ static const struct r600_reg si_context_reg_list[] = {
{R_028810_PA_CL_CLIP_CNTL, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0},
{R_02881C_PA_CL_VS_OUT_CNTL, 0},
{R_028820_PA_CL_NANINF_CNTL, 0},
{R_028824_PA_SU_LINE_STIPPLE_CNTL, 0},
{R_028828_PA_SU_LINE_STIPPLE_SCALE, 0},
{R_02882C_PA_SU_PRIM_FILTER_CNTL, 0},
{R_028A00_PA_SU_POINT_SIZE, 0},
{R_028A04_PA_SU_POINT_MINMAX, 0},
{R_028A08_PA_SU_LINE_CNTL, 0},
{R_028A0C_PA_SC_LINE_STIPPLE, 0},
{R_028A10_VGT_OUTPUT_PATH_CNTL, 0},
{R_028A14_VGT_HOS_CNTL, 0},
@ -141,7 +135,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0},
{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0},
{R_028A40_VGT_GS_MODE, 0},
{R_028A48_PA_SC_MODE_CNTL_0, 0},
{R_028A4C_PA_SC_MODE_CNTL_1, 0},
{R_028A50_VGT_ENHANCE, 0},
{R_028A54_VGT_GS_PER_ES, 0},
@ -168,7 +161,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_028B54_VGT_SHADER_STAGES_EN, 0},
{R_028B70_DB_ALPHA_TO_MASK, 0},
{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0},
{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0},
{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0},
{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0},
{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0},
@ -177,12 +169,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0},
{R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0},
{R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0},
{R_028BDC_PA_SC_LINE_CNTL, 0},
{R_028BE4_PA_SU_VTX_CNTL, 0},
{R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0},
{R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0},
{R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0},
{R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0},
{R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0},
{R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, 0},
{R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0},

135
src/gallium/drivers/radeonsi/evergreen_state.c
View file

@ -76,21 +76,6 @@ static uint32_t r600_translate_stencil_op(int s_op)
}
#endif
static uint32_t si_translate_fill(uint32_t func)
{
switch(func) {
case PIPE_POLYGON_MODE_FILL:
return V_028814_X_DRAW_TRIANGLES;
case PIPE_POLYGON_MODE_LINE:
return V_028814_X_DRAW_LINES;
case PIPE_POLYGON_MODE_POINT:
return V_028814_X_DRAW_POINTS;
default:
assert(0);
return V_028814_X_DRAW_POINTS;
}
}
/* translates straight */
static uint32_t si_translate_ds_func(int func)
{
@ -838,113 +823,6 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
return rstate;
}
static void *evergreen_create_rs_state(struct pipe_context *ctx,
const struct pipe_rasterizer_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
struct r600_pipe_state *rstate;
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
unsigned clip_rule;
float psize_min, psize_max;
if (rs == NULL) {
return NULL;
}
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
if (state->flatshade_first)
prov_vtx = 0;
rstate = &rs->rstate;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
rs->pa_sc_line_stipple = state->line_stipple_enable ?
S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_su_sc_mode_cntl =
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
rs->pa_cl_clip_cntl =
S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
rs->pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
/* offset */
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 12.0f;
rstate->id = R600_PIPE_STATE_RASTERIZER;
/* XXX: Flat shading hangs the GPU */
tmp = S_0286D4_FLAT_SHADE_ENA(0);
if (state->sprite_coord_enable) {
tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
}
}
r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);
r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
psize_max = 8192;
} else {
/* Force the point size to be as if the vertex output was disabled. */
psize_min = state->point_size;
psize_max = state->point_size;
}
/* Divide by two, because 0.5 = 1 pixel. */
r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
NULL, 0);
tmp = (unsigned)state->line_width * 8;
r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BDC_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BE4_PA_SU_VTX_CNTL,
S_028BE4_PIX_CENTER(state->gl_rasterization_rules),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
return rstate;
}
static void *si_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
@ -1259,7 +1137,6 @@ void cayman_init_state_functions(struct r600_context *rctx)
si_init_state_functions(rctx);
rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
rctx->context.create_fs_state = si_create_shader_state;
rctx->context.create_rasterizer_state = evergreen_create_rs_state;
rctx->context.create_sampler_state = si_create_sampler_state;
rctx->context.create_sampler_view = evergreen_create_sampler_view;
rctx->context.create_vertex_elements_state = si_create_vertex_elements;
@ -1267,13 +1144,11 @@ void cayman_init_state_functions(struct r600_context *rctx)
rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
rctx->context.bind_fs_state = r600_bind_ps_shader;
rctx->context.bind_rasterizer_state = r600_bind_rs_state;
rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
rctx->context.bind_vs_state = r600_bind_vs_shader;
rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
rctx->context.delete_fs_state = r600_delete_ps_shader;
rctx->context.delete_rasterizer_state = r600_delete_rs_state;
rctx->context.delete_sampler_state = si_delete_sampler_state;
rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
rctx->context.delete_vs_state = r600_delete_vs_shader;
@ -1337,8 +1212,8 @@ void cayman_polygon_offset_update(struct r600_context *rctx)
state.id = R600_PIPE_STATE_POLYGON_OFFSET;
state.nregs = 0;
if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
float offset_units = rctx->rasterizer->offset_units;
if (rctx->queued.named.rasterizer && rctx->framebuffer.zsbuf) {
float offset_units = rctx->queued.named.rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
switch (rctx->framebuffer.zsbuf->texture->format) {
@ -1364,13 +1239,13 @@ void cayman_polygon_offset_update(struct r600_context *rctx)
offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
r600_pipe_state_add_reg(&state,
R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
fui(rctx->rasterizer->offset_scale), NULL, 0);
fui(rctx->queued.named.rasterizer->offset_scale), NULL, 0);
r600_pipe_state_add_reg(&state,
R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
fui(offset_units), NULL, 0);
r600_pipe_state_add_reg(&state,
R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
fui(rctx->rasterizer->offset_scale), NULL, 0);
fui(rctx->queued.named.rasterizer->offset_scale), NULL, 0);
r600_pipe_state_add_reg(&state,
R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
fui(offset_units), NULL, 0);
@ -1405,7 +1280,7 @@ void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
/* XXX: Flat shading hangs the GPU */
if (rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
rctx->rasterizer->flatshade))
rctx->queued.named.rasterizer->flatshade))
have_linear = TRUE;
if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
have_linear = TRUE;

2
src/gallium/drivers/radeonsi/r600_blit.c
View file

@ -53,7 +53,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
}
util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
util_blitter_save_rasterizer(rctx->blitter, rctx->queued.named.rasterizer);
util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);

38
src/gallium/drivers/radeonsi/r600_state_common.c
View file

@ -195,44 +195,6 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
r600_set_stencil_ref(ctx, &ref);
}
void r600_bind_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
struct r600_context *rctx = (struct r600_context *)ctx;
if (state == NULL)
return;
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
rctx->rasterizer = rs;
rctx->states[rs->rstate.id] = &rs->rstate;
r600_context_pipe_state_set(rctx, &rs->rstate);
if (rctx->chip_class >= CAYMAN) {
cayman_polygon_offset_update(rctx);
}
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
if (rctx->rasterizer == rs) {
rctx->rasterizer = NULL;
}
if (rctx->states[rs->rstate.id] == &rs->rstate) {
rctx->states[rs->rstate.id] = NULL;
}
free(rs);
}
void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state)
{

16
src/gallium/drivers/radeonsi/radeonsi_pipe.h
View file

@ -77,7 +77,6 @@ struct r600_atom_surface_sync {
enum r600_pipe_state_id {
R600_PIPE_STATE_CONFIG,
R600_PIPE_STATE_SEAMLESS_CUBEMAP,
R600_PIPE_STATE_RASTERIZER,
R600_PIPE_STATE_VGT,
R600_PIPE_STATE_DSA,
R600_PIPE_STATE_STENCIL_REF,
@ -121,18 +120,6 @@ struct si_pipe_sampler_state {
uint32_t val[4];
};
struct r600_pipe_rasterizer {
struct r600_pipe_state rstate;
boolean flatshade;
unsigned sprite_coord_enable;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
unsigned pa_cl_vs_out_cntl;
float offset_units;
float offset_scale;
};
struct r600_pipe_dsa {
struct r600_pipe_state rstate;
unsigned alpha_ref;
@ -243,7 +230,6 @@ struct r600_context {
struct r600_pipe_state vs_const_buffer;
struct r600_pipe_state vs_user_data;
struct r600_pipe_state ps_const_buffer;
struct r600_pipe_rasterizer *rasterizer;
struct r600_pipe_state vgt;
struct r600_pipe_state spi;
struct pipe_query *current_render_cond;
@ -404,8 +390,6 @@ void *si_create_vertex_elements(struct pipe_context *ctx,
const struct pipe_vertex_element *elements);
void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
void r600_bind_rs_state(struct pipe_context *ctx, void *state);
void r600_delete_rs_state(struct pipe_context *ctx, void *state);
void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state);
void r600_delete_state(struct pipe_context *ctx, void *state);

3
src/gallium/drivers/radeonsi/radeonsi_shader.c
View file

@ -12,6 +12,7 @@
#include "radeonsi_pipe.h"
#include "radeonsi_shader.h"
#include "si_state.h"
#include "sid.h"
#include <assert.h>
@ -251,7 +252,7 @@ static void declare_input_fs(
switch (decl->Interp.Interpolate) {
case TGSI_INTERPOLATE_COLOR:
/* XXX: Flat shading hangs the GPU */
if (si_shader_ctx->rctx->rasterizer->flatshade) {
if (si_shader_ctx->rctx->queued.named.rasterizer->flatshade) {
#if 0
intr_name = "llvm.SI.fs.interp.constant";
#else

153
src/gallium/drivers/radeonsi/si_state.c
View file

@ -270,6 +270,155 @@ static void si_set_viewport_state(struct pipe_context *ctx,
si_pm4_set_state(rctx, viewport, viewport);
}
/*
* Rasterizer
*/
static uint32_t si_translate_fill(uint32_t func)
{
switch(func) {
case PIPE_POLYGON_MODE_FILL:
return V_028814_X_DRAW_TRIANGLES;
case PIPE_POLYGON_MODE_LINE:
return V_028814_X_DRAW_LINES;
case PIPE_POLYGON_MODE_POINT:
return V_028814_X_DRAW_POINTS;
default:
assert(0);
return V_028814_X_DRAW_POINTS;
}
}
static void *si_create_rs_state(struct pipe_context *ctx,
const struct pipe_rasterizer_state *state)
{
struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
struct si_pm4_state *pm4 = &rs->pm4;
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
unsigned clip_rule;
float psize_min, psize_max;
if (rs == NULL) {
return NULL;
}
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
if (state->flatshade_first)
prov_vtx = 0;
rs->flatshade = state->flatshade;
rs->sprite_coord_enable = state->sprite_coord_enable;
rs->pa_sc_line_stipple = state->line_stipple_enable ?
S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
rs->pa_su_sc_mode_cntl =
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
rs->pa_cl_clip_cntl =
S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
rs->pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
/* offset */
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 12.0f;
/* XXX: Flat shading hangs the GPU */
tmp = S_0286D4_FLAT_SHADE_ENA(0);
if (state->sprite_coord_enable) {
tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
}
}
si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
/* point size 12.4 fixed point */
tmp = (unsigned)(state->point_size * 8.0);
si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
psize_max = 8192;
} else {
/* Force the point size to be as if the vertex output was disabled. */
psize_min = state->point_size;
psize_max = state->point_size;
}
/* Divide by two, because 0.5 = 1 pixel. */
si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
tmp = (unsigned)state->line_width * 8;
si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
return rs;
}
static void si_bind_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
if (state == NULL)
return;
// TODO
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
si_pm4_bind_state(rctx, rasterizer, rs);
if (rctx->chip_class >= CAYMAN) {
cayman_polygon_offset_update(rctx);
}
}
static void si_delete_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
}
/*
* format translation
*/
@ -933,6 +1082,10 @@ void si_init_state_functions(struct r600_context *rctx)
rctx->context.delete_blend_state = si_delete_blend_state;
rctx->context.set_blend_color = si_set_blend_color;
rctx->context.create_rasterizer_state = si_create_rs_state;
rctx->context.bind_rasterizer_state = si_bind_rs_state;
rctx->context.delete_rasterizer_state = si_delete_rs_state;
rctx->context.set_clip_state = si_set_clip_state;
rctx->context.set_scissor_state = si_set_scissor_state;
rctx->context.set_viewport_state = si_set_viewport_state;

13
src/gallium/drivers/radeonsi/si_state.h
View file

@ -40,6 +40,18 @@ struct si_state_viewport {
struct pipe_viewport_state viewport;
};
struct si_state_rasterizer {
struct si_pm4_state pm4;
bool flatshade;
unsigned sprite_coord_enable;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
unsigned pa_cl_vs_out_cntl;
float offset_units;
float offset_scale;
};
union si_state {
struct {
struct si_state_blend *blend;
@ -48,6 +60,7 @@ union si_state {
struct si_pm4_state *scissor;
struct si_state_viewport *viewport;
struct si_pm4_state *framebuffer;
struct si_state_rasterizer *rasterizer;
} named;
struct si_pm4_state *array[0];
};