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r600g: use SX_MISC to implement rasterizer discard

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Yeah I am reworking it again. This is way simpler than the other methods.
This commit is contained in:
Marek Olšák 2012-03-07 17:15:23 +01:00
parent c7eaf274a9
commit f6546535c9
4 changed files with 13 additions and 4 deletions
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1
src/gallium/drivers/r600/evergreen_state.c
View file

@ -903,6 +903,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard), NULL, 0);
return rstate;
}

3
src/gallium/drivers/r600/evergreend.h
View file

@ -1590,6 +1590,9 @@
#define R_028238_CB_TARGET_MASK 0x00028238
#define R_02823C_CB_SHADER_MASK 0x0002823C
#define R_028350_SX_MISC 0x00028350
#define S_028350_MULTIPASS(x) (((x) & 0x1) << 0)
#define G_028350_MULTIPASS(x) (((x) >> 0) & 0x1)
#define C_028350_MULTIPASS 0xFFFFFFFE
#define R_028354_SX_SURFACE_SYNC 0x00028354
#define S_028354_SURFACE_SYNC_MASK(x) (((x) & 0x1FF) << 0)
#define R_028380_SQ_VTX_SEMANTIC_0 0x00028380

6
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -423,6 +423,7 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028E74_PA_CL_UCP5_Y, 0, 0},
{R_028E78_PA_CL_UCP5_Z, 0, 0},
{R_028E7C_PA_CL_UCP5_W, 0, 0},
{R_028350_SX_MISC, 0, 0},
{R_028380_SQ_VTX_SEMANTIC_0, 0, 0},
{R_028384_SQ_VTX_SEMANTIC_1, 0, 0},
{R_028388_SQ_VTX_SEMANTIC_2, 0, 0},
@ -1237,6 +1238,11 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
if (ctx->chip_class <= R700) {
r600_write_context_reg(cs, R_028350_SX_MISC, 0);
}
/* force to keep tiling flags */
flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;

7
src/gallium/drivers/r600/r600_state.c
View file

@ -908,8 +908,8 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
@ -918,6 +918,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard), NULL, 0);
return rstate;
}
@ -1990,8 +1991,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
r600_store_context_reg(cb, R_028350_SX_MISC, 0);
if (rctx->chip_class >= R700) {
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);