From f650c2b076e4e421f0df576ee844655c2b220545 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 8 Nov 2021 11:05:33 +1000 Subject: [PATCH] nvc0: fix ga10x compute launch Signed-off-by: Ben Skeggs Acked-by: M Henning Reviewed-by: Adam Jackson Reviewed-by: Karol Herbst Part-of: --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c index 9e38ff95283..9af2601b335 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c @@ -883,8 +883,14 @@ nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info) PUSH_REF1(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD); BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1); PUSH_DATA (push, desc_gpuaddr >> 8); - BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1); - PUSH_DATA (push, 0x3); + if (screen->compute->oclass < GA102_COMPUTE_CLASS) { + BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1); + PUSH_DATA (push, 0x3); + } else { + BEGIN_NIC0(push, SUBC_CP(0x02c0), 2); + PUSH_DATA (push, 1); + PUSH_DATA (push, 2); + } BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1); PUSH_DATA (push, 0);