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radv: emit db_htile_surface reg on gfx9 as well

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This is also a GFX9 register.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 674ecbfef2)
This commit is contained in:
David Airlie 2017-08-15 14:20:16 +10:00 • committed by Emil Velikov
parent f70f216564
commit f60ff71b6f
1 changed files with 2 additions and 1 deletions
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3
src/amd/vulkan/radv_cmd_buffer.c
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@ -1007,6 +1007,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
}
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
@ -1043,7 +1045,6 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
}
radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,