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all: rename PIPE_SHADER_COMPUTE to MESA_SHADER_COMPUTE

Browse source 
Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/PIPE_SHADER_COMPUTE/MESA_SHADER_COMPUTE/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
Qiang Yu 2025-08-05 13:51:02 +08:00
parent 11027dd3f8
commit f60ea0a3cd
127 changed files with 448 additions and 448 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/asahi/vulkan/hk_cmd_buffer.c
View file

@ -682,7 +682,7 @@ hk_upload_usc_words(struct hk_cmd_buffer *cmd, struct hk_shader *s,
uint64_t root_ptr;
if (sw_stage == PIPE_SHADER_COMPUTE) {
if (sw_stage == MESA_SHADER_COMPUTE) {
root_ptr = hk_cmd_buffer_upload_root(cmd, VK_PIPELINE_BIND_POINT_COMPUTE);
} else {
root_ptr = cmd->state.gfx.root;

2
src/compiler/shader_enums.h
View file

@ -65,7 +65,7 @@ typedef enum pipe_shader_type
MESA_SHADER_COMPUTE = 5,
PIPE_SHADER_COMPUTE = MESA_SHADER_COMPUTE,
PIPE_SHADER_TYPES = (PIPE_SHADER_COMPUTE + 1),
PIPE_SHADER_TYPES = (MESA_SHADER_COMPUTE + 1),
/* Vulkan-only stages. */
MESA_SHADER_TASK = 6,
PIPE_SHADER_TASK = MESA_SHADER_TASK,

12
src/gallium/auxiliary/cso_cache/cso_context.c
View file

@ -318,9 +318,9 @@ cso_create_context(struct pipe_context *pipe, unsigned flags)
if (pipe->screen->shader_caps[MESA_SHADER_TESS_CTRL].max_instructions > 0) {
ctx->has_tessellation = true;
}
if (pipe->screen->shader_caps[PIPE_SHADER_COMPUTE].max_instructions > 0) {
if (pipe->screen->shader_caps[MESA_SHADER_COMPUTE].max_instructions > 0) {
int supported_irs =
pipe->screen->shader_caps[PIPE_SHADER_COMPUTE].supported_irs;
pipe->screen->shader_caps[MESA_SHADER_COMPUTE].supported_irs;
if (supported_irs & ((1 << PIPE_SHADER_IR_TGSI) |
(1 << PIPE_SHADER_IR_NIR))) {
ctx->has_compute_shader = true;
@ -375,7 +375,7 @@ cso_unbind_context(struct cso_context *cso)
if (!ctx->has_tessellation)
continue;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
if (!ctx->has_compute_shader)
continue;
break;
@ -1141,7 +1141,7 @@ cso_restore_compute_shader(struct cso_context_priv *ctx)
static void
cso_save_compute_samplers(struct cso_context_priv *ctx)
{
struct sampler_info *info = &ctx->samplers[PIPE_SHADER_COMPUTE];
struct sampler_info *info = &ctx->samplers[MESA_SHADER_COMPUTE];
struct sampler_info *saved = &ctx->compute_samplers_saved;
memcpy(saved->cso_samplers, info->cso_samplers,
@ -1153,7 +1153,7 @@ cso_save_compute_samplers(struct cso_context_priv *ctx)
static void
cso_restore_compute_samplers(struct cso_context_priv *ctx)
{
struct sampler_info *info = &ctx->samplers[PIPE_SHADER_COMPUTE];
struct sampler_info *info = &ctx->samplers[MESA_SHADER_COMPUTE];
struct sampler_info *saved = &ctx->compute_samplers_saved;
memcpy(info->cso_samplers, saved->cso_samplers,
@ -1167,7 +1167,7 @@ cso_restore_compute_samplers(struct cso_context_priv *ctx)
}
}
cso_single_sampler_done(&ctx->base, PIPE_SHADER_COMPUTE);
cso_single_sampler_done(&ctx->base, MESA_SHADER_COMPUTE);
}

6
src/gallium/auxiliary/driver_ddebug/dd_draw.c
View file

@ -269,7 +269,7 @@ dd_dump_shader(struct dd_draw_state *dstate, enum pipe_shader_type sh, FILE *f)
shader_str[MESA_SHADER_TESS_EVAL] = "TESS_EVAL";
shader_str[MESA_SHADER_GEOMETRY] = "GEOMETRY";
shader_str[MESA_SHADER_FRAGMENT] = "FRAGMENT";
shader_str[PIPE_SHADER_COMPUTE] = "COMPUTE";
shader_str[MESA_SHADER_COMPUTE] = "COMPUTE";
if (sh == MESA_SHADER_TESS_CTRL &&
!dstate->shaders[MESA_SHADER_TESS_CTRL] &&
@ -404,7 +404,7 @@ dd_dump_draw_vbo(struct dd_draw_state *dstate, struct pipe_draw_info *info,
fprintf(f, "\n");
for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
if (sh == PIPE_SHADER_COMPUTE)
if (sh == MESA_SHADER_COMPUTE)
continue;
dd_dump_shader(dstate, sh, f);
@ -446,7 +446,7 @@ dd_dump_launch_grid(struct dd_draw_state *dstate, struct pipe_grid_info *info, F
DUMP(grid_info, info);
fprintf(f, "\n");
dd_dump_shader(dstate, PIPE_SHADER_COMPUTE, f);
dd_dump_shader(dstate, MESA_SHADER_COMPUTE, f);
fprintf(f, "\n");
}

4
src/gallium/auxiliary/tgsi/tgsi_exec.c
View file

@ -1220,7 +1220,7 @@ tgsi_exec_machine_create(enum pipe_shader_type shader_type)
mach->ShaderType = shader_type;
if (shader_type != PIPE_SHADER_COMPUTE) {
if (shader_type != MESA_SHADER_COMPUTE) {
mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_INPUTS, 16);
mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_SHADER_OUTPUTS, 16);
if (!mach->Inputs || !mach->Outputs)
@ -6028,7 +6028,7 @@ tgsi_exec_machine_run( struct tgsi_exec_machine *mach, int start_pc )
barrier_hit = exec_instruction(mach, mach->Instructions + mach->pc, &mach->pc);
/* for compute shaders if we hit a barrier return now for later rescheduling */
if (barrier_hit && mach->ShaderType == PIPE_SHADER_COMPUTE)
if (barrier_hit && mach->ShaderType == MESA_SHADER_COMPUTE)
return 0;
#if DEBUG_EXECUTION

2
src/gallium/auxiliary/tgsi/tgsi_from_mesa.h
View file

@ -66,7 +66,7 @@ pipe_shader_type_from_mesa(gl_shader_stage stage)
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_TESS_CTRL == MESA_SHADER_TESS_CTRL);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_TESS_EVAL == MESA_SHADER_TESS_EVAL);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_GEOMETRY == MESA_SHADER_GEOMETRY);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_COMPUTE == PIPE_SHADER_COMPUTE);
STATIC_ASSERT((enum pipe_shader_type) MESA_SHADER_COMPUTE == MESA_SHADER_COMPUTE);
return (enum pipe_shader_type)stage;
}

4
src/gallium/auxiliary/tgsi/tgsi_scan.c
View file

@ -85,7 +85,7 @@ scan_src_operand(struct tgsi_shader_info *info,
{
int ind = src->Register.Index;
if (info->processor == PIPE_SHADER_COMPUTE &&
if (info->processor == MESA_SHADER_COMPUTE &&
src->Register.File == TGSI_FILE_SYSTEM_VALUE) {
unsigned name;
@ -615,7 +615,7 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
procType == MESA_SHADER_GEOMETRY ||
procType == MESA_SHADER_TESS_CTRL ||
procType == MESA_SHADER_TESS_EVAL ||
procType == PIPE_SHADER_COMPUTE);
procType == MESA_SHADER_COMPUTE);
info->processor = procType;
if (procType == MESA_SHADER_GEOMETRY)

2
src/gallium/auxiliary/tgsi/tgsi_text.c
View file

@ -343,7 +343,7 @@ static bool parse_header( struct translate_ctx *ctx )
else if (str_match_nocase_whole( &ctx->cur, "TESS_EVAL" ))
processor = MESA_SHADER_TESS_EVAL;
else if (str_match_nocase_whole( &ctx->cur, "COMP" ))
processor = PIPE_SHADER_COMPUTE;
processor = MESA_SHADER_COMPUTE;
else {
report_error( ctx, "Unknown header" );
return false;

2
src/gallium/auxiliary/util/u_tests.c
View file

@ -843,7 +843,7 @@ test_compute_clear_image_shader(struct pipe_context *ctx)
image.shader_access = image.access = PIPE_IMAGE_ACCESS_READ_WRITE;
image.format = cb->format;
ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, 0, &image);
ctx->set_shader_images(ctx, MESA_SHADER_COMPUTE, 0, 1, 0, &image);
/* Dispatch compute. */
struct pipe_grid_info info = {0};

6
src/gallium/auxiliary/util/u_threaded_context.c
View file

@ -932,7 +932,7 @@ tc_add_all_compute_bindings_to_buffer_list(struct threaded_context *tc)
{
BITSET_WORD *buffer_list = tc->buffer_lists[tc->next_buf_list].buffer_list;
tc_add_shader_bindings_to_buffer_list(tc, buffer_list, PIPE_SHADER_COMPUTE);
tc_add_shader_bindings_to_buffer_list(tc, buffer_list, MESA_SHADER_COMPUTE);
tc->add_all_compute_bindings_to_buffer_list = false;
}
@ -964,7 +964,7 @@ tc_rebind_buffer(struct threaded_context *tc, uint32_t old_id, uint32_t new_id,
if (tc->seen_gs)
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, MESA_SHADER_GEOMETRY, rebind_mask);
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, PIPE_SHADER_COMPUTE, rebind_mask);
rebound += tc_rebind_shader_bindings(tc, old_id, new_id, MESA_SHADER_COMPUTE, rebind_mask);
if (rebound)
BITSET_SET(tc->buffer_lists[tc->next_buf_list].buffer_list, new_id & TC_BUFFER_ID_MASK);
@ -1008,7 +1008,7 @@ tc_is_buffer_bound_for_write(struct threaded_context *tc, uint32_t id)
if (tc_is_buffer_shader_bound_for_write(tc, id, MESA_SHADER_VERTEX) ||
tc_is_buffer_shader_bound_for_write(tc, id, MESA_SHADER_FRAGMENT) ||
tc_is_buffer_shader_bound_for_write(tc, id, PIPE_SHADER_COMPUTE))
tc_is_buffer_shader_bound_for_write(tc, id, MESA_SHADER_COMPUTE))
return true;
if (tc->seen_tcs &&

18
src/gallium/auxiliary/vl/vl_compositor_cs.c
View file

@ -100,7 +100,7 @@ static nir_def *cs_create_shader(struct vl_compositor *c, struct cs_shader *s)
glsl_sampler_type(sampler_dim, /*is_shadow*/ false, s->array, GLSL_TYPE_FLOAT);
const struct glsl_type *image_type =
glsl_image_type(GLSL_SAMPLER_DIM_2D, /*is_array*/ false, GLSL_TYPE_FLOAT);
const nir_shader_compiler_options *options = c->pipe->screen->nir_options[PIPE_SHADER_COMPUTE];
const nir_shader_compiler_options *options = c->pipe->screen->nir_options[MESA_SHADER_COMPUTE];
s->b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, options, "vl:%s", s->name);
nir_builder *b = &s->b;
@ -615,7 +615,7 @@ cs_launch(struct vl_compositor *c,
image.shader_access = image.access = PIPE_IMAGE_ACCESS_READ_WRITE;
image.format = c->fb_state.cbufs[0].texture->format;
ctx->set_shader_images(c->pipe, PIPE_SHADER_COMPUTE, 0, 1, 0, &image);
ctx->set_shader_images(c->pipe, MESA_SHADER_COMPUTE, 0, 1, 0, &image);
/* Bind compute shader */
ctx->bind_compute_state(ctx, cs);
@ -854,20 +854,20 @@ draw_layers(struct vl_compositor *c,
calc_proj(layer, sampler1->texture, drawn.chroma_proj);
set_viewport(s, &drawn, samplers);
c->pipe->bind_sampler_states(c->pipe, PIPE_SHADER_COMPUTE, 0,
c->pipe->bind_sampler_states(c->pipe, MESA_SHADER_COMPUTE, 0,
num_sampler_views, layer->samplers);
c->pipe->set_sampler_views(c->pipe, PIPE_SHADER_COMPUTE, 0,
c->pipe->set_sampler_views(c->pipe, MESA_SHADER_COMPUTE, 0,
num_sampler_views, 0, samplers);
cs_launch(c, layer->cs, &(drawn.area));
/* Unbind. */
c->pipe->set_shader_images(c->pipe, PIPE_SHADER_COMPUTE, 0, 0, 1, NULL);
c->pipe->set_constant_buffer(c->pipe, PIPE_SHADER_COMPUTE, 0, false, NULL);
c->pipe->set_sampler_views(c->pipe, PIPE_SHADER_COMPUTE, 0, 0,
c->pipe->set_shader_images(c->pipe, MESA_SHADER_COMPUTE, 0, 0, 1, NULL);
c->pipe->set_constant_buffer(c->pipe, MESA_SHADER_COMPUTE, 0, false, NULL);
c->pipe->set_sampler_views(c->pipe, MESA_SHADER_COMPUTE, 0, 0,
num_sampler_views, NULL);
c->pipe->bind_compute_state(c->pipe, NULL);
c->pipe->bind_sampler_states(c->pipe, PIPE_SHADER_COMPUTE, 0,
c->pipe->bind_sampler_states(c->pipe, MESA_SHADER_COMPUTE, 0,
num_sampler_views, NULL);
if (dirty) {
@ -910,7 +910,7 @@ vl_compositor_cs_render(struct vl_compositor_state *s,
dirty_area->x1 = dirty_area->y1 = VL_COMPOSITOR_MIN_DIRTY;
}
pipe_set_constant_buffer(c->pipe, PIPE_SHADER_COMPUTE, 0, s->shader_params);
pipe_set_constant_buffer(c->pipe, MESA_SHADER_COMPUTE, 0, s->shader_params);
draw_layers(c, s, dirty_area);
}

8
src/gallium/auxiliary/vl/vl_deint_filter_cs.c
View file

@ -33,7 +33,7 @@ create_deint_shader(struct vl_deint_filter *filter, unsigned field)
glsl_sampler_type(GLSL_SAMPLER_DIM_RECT, false, false, GLSL_TYPE_FLOAT);
const struct glsl_type *image_type =
glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
const nir_shader_compiler_options *options = filter->pipe->screen->nir_options[PIPE_SHADER_COMPUTE];
const nir_shader_compiler_options *options = filter->pipe->screen->nir_options[MESA_SHADER_COMPUTE];
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, options, "vl:deint");
b.shader->info.workgroup_size[0] = 8;
@ -213,7 +213,7 @@ vl_deint_filter_cs_render(struct vl_deint_filter *filter,
prev_sv = prev->get_sampler_view_planes(prev);
next_sv = next->get_sampler_view_planes(next);
filter->pipe->bind_sampler_states(filter->pipe, PIPE_SHADER_COMPUTE,
filter->pipe->bind_sampler_states(filter->pipe, MESA_SHADER_COMPUTE,
0, 4, filter->sampler);
for (unsigned i = 0; i < 2; i++) {
@ -224,7 +224,7 @@ vl_deint_filter_cs_render(struct vl_deint_filter *filter,
sampler_views[1] = prev_sv[i];
sampler_views[2] = cur_sv[i];
sampler_views[3] = next_sv[i];
filter->pipe->set_sampler_views(filter->pipe, PIPE_SHADER_COMPUTE,
filter->pipe->set_sampler_views(filter->pipe, MESA_SHADER_COMPUTE,
0, 4, 0, sampler_views);
/* Bind the image */
@ -234,7 +234,7 @@ vl_deint_filter_cs_render(struct vl_deint_filter *filter,
.shader_access = PIPE_IMAGE_ACCESS_WRITE,
.format = dst->texture->format,
};
filter->pipe->set_shader_images(filter->pipe, PIPE_SHADER_COMPUTE,
filter->pipe->set_shader_images(filter->pipe, MESA_SHADER_COMPUTE,
0, 1, 0, &image);
/* Bind compute shader */

26
src/gallium/drivers/asahi/agx_blit.c
View file

@ -57,7 +57,7 @@ static void *
asahi_blit_compute_shader(struct pipe_context *ctx, struct asahi_blit_key *key)
{
const nir_shader_compiler_options *options =
ctx->screen->nir_options[PIPE_SHADER_COMPUTE];
ctx->screen->nir_options[MESA_SHADER_COMPUTE];
nir_builder b_ =
nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, options, "blit_cs");
@ -244,7 +244,7 @@ static void
asahi_compute_save(struct agx_context *ctx)
{
struct asahi_blitter *blitter = &ctx->compute_blitter;
struct agx_stage *stage = &ctx->stage[PIPE_SHADER_COMPUTE];
struct agx_stage *stage = &ctx->stage[MESA_SHADER_COMPUTE];
assert(!blitter->active && "recursion detected, driver bug");
@ -278,25 +278,25 @@ asahi_compute_restore(struct agx_context *ctx)
struct asahi_blitter *blitter = &ctx->compute_blitter;
if (blitter->has_saved_image) {
pctx->set_shader_images(pctx, PIPE_SHADER_COMPUTE, 0, 1, 0,
pctx->set_shader_images(pctx, MESA_SHADER_COMPUTE, 0, 1, 0,
&blitter->saved_image);
pipe_resource_reference(&blitter->saved_image.resource, NULL);
}
/* take_ownership=true so do not unreference */
pctx->set_constant_buffer(pctx, PIPE_SHADER_COMPUTE, 0, true,
pctx->set_constant_buffer(pctx, MESA_SHADER_COMPUTE, 0, true,
&blitter->saved_cb);
blitter->saved_cb.buffer = NULL;
if (blitter->saved_sampler_view) {
pctx->set_sampler_views(pctx, PIPE_SHADER_COMPUTE, 0, 1, 0,
pctx->set_sampler_views(pctx, MESA_SHADER_COMPUTE, 0, 1, 0,
&blitter->saved_sampler_view);
blitter->saved_sampler_view = NULL;
}
if (blitter->saved_num_sampler_states) {
pctx->bind_sampler_states(pctx, PIPE_SHADER_COMPUTE, 0,
pctx->bind_sampler_states(pctx, MESA_SHADER_COMPUTE, 0,
blitter->saved_num_sampler_states,
blitter->saved_sampler_states);
}
@ -366,7 +366,7 @@ asahi_compute_blit(struct pipe_context *ctx, const struct pipe_blit_info *info,
.buffer_size = sizeof(data),
.user_buffer = data,
};
ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, false, &cb);
ctx->set_constant_buffer(ctx, MESA_SHADER_COMPUTE, 0, false, &cb);
struct pipe_image_view image = {
.resource = dst,
@ -378,7 +378,7 @@ asahi_compute_blit(struct pipe_context *ctx, const struct pipe_blit_info *info,
.u.tex.last_layer = info->dst.box.z + depth - 1,
.u.tex.single_layer_view = !array,
};
ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, 0, &image);
ctx->set_shader_images(ctx, MESA_SHADER_COMPUTE, 0, 1, 0, &image);
if (!blitter->sampler[info->filter]) {
struct pipe_sampler_state sampler_state = {
@ -396,7 +396,7 @@ asahi_compute_blit(struct pipe_context *ctx, const struct pipe_blit_info *info,
ctx->create_sampler_state(ctx, &sampler_state);
}
ctx->bind_sampler_states(ctx, PIPE_SHADER_COMPUTE, 0, 1,
ctx->bind_sampler_states(ctx, MESA_SHADER_COMPUTE, 0, 1,
&blitter->sampler[info->filter]);
/* Initialize the sampler view. */
@ -412,7 +412,7 @@ asahi_compute_blit(struct pipe_context *ctx, const struct pipe_blit_info *info,
src_templ.u.tex.first_level = info->src.level;
src_templ.u.tex.last_level = info->src.level;
src_view = ctx->create_sampler_view(ctx, src, &src_templ);
ctx->set_sampler_views(ctx, PIPE_SHADER_COMPUTE, 0, 1, 0, &src_view);
ctx->set_sampler_views(ctx, MESA_SHADER_COMPUTE, 0, 1, 0, &src_view);
ctx->sampler_view_release(ctx, src_view);
struct asahi_blit_key key = {
@ -447,9 +447,9 @@ asahi_compute_blit(struct pipe_context *ctx, const struct pipe_blit_info *info,
},
};
ctx->launch_grid(ctx, &grid_info);
ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 0, 1, NULL);
ctx->set_constant_buffer(ctx, PIPE_SHADER_COMPUTE, 0, false, NULL);
ctx->set_sampler_views(ctx, PIPE_SHADER_COMPUTE, 0, 0, 1, NULL);
ctx->set_shader_images(ctx, MESA_SHADER_COMPUTE, 0, 0, 1, NULL);
ctx->set_constant_buffer(ctx, MESA_SHADER_COMPUTE, 0, false, NULL);
ctx->set_sampler_views(ctx, MESA_SHADER_COMPUTE, 0, 0, 1, NULL);
asahi_compute_restore(agx_context(ctx));
}

2
src/gallium/drivers/asahi/agx_nir_lower_sysvals.c
View file

@ -411,7 +411,7 @@ lay_out_uniforms(struct agx_compiled_shader *shader, struct state *state)
.length = 4,
};
bool sw = state->hw_stage == PIPE_SHADER_COMPUTE;
bool sw = state->hw_stage == MESA_SHADER_COMPUTE;
if (sw) {
shader->push[shader->push_range_count++] = (struct agx_push_range){
.uniform = AGX_ABI_VUNI_INPUT_ASSEMBLY(count),

2
src/gallium/drivers/asahi/agx_pipe.c
View file

@ -1864,7 +1864,7 @@ agx_init_shader_caps(struct pipe_screen *pscreen)
{
bool is_no16 = agx_device(pscreen)->debug & AGX_DBG_NO16;
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&pscreen->shader_caps[i];

16
src/gallium/drivers/asahi/agx_state.c
View file

@ -1658,7 +1658,7 @@ agx_compile_variant(struct agx_device *dev, struct pipe_context *pctx,
if (pre_gs) {
compiled->pre_gs =
agx_compile_nir(dev, pre_gs, &pctx->debug, PIPE_SHADER_COMPUTE, false,
agx_compile_nir(dev, pre_gs, &pctx->debug, MESA_SHADER_COMPUTE, false,
true, false, 0, NULL);
}
@ -2439,7 +2439,7 @@ agx_bind_tes_state(struct pipe_context *pctx, void *cso)
static void
agx_bind_cs_state(struct pipe_context *pctx, void *cso)
{
agx_bind_shader_state(pctx, cso, PIPE_SHADER_COMPUTE);
agx_bind_shader_state(pctx, cso, MESA_SHADER_COMPUTE);
}
/* Forward declare because of the recursion hit with geometry shaders */
@ -2605,7 +2605,7 @@ agx_build_meta_shader_internal(struct agx_context *ctx,
}
struct agx_compiled_shader *shader = agx_compile_nir(
dev, b.shader, NULL, PIPE_SHADER_COMPUTE, internal_kernel,
dev, b.shader, NULL, MESA_SHADER_COMPUTE, internal_kernel,
!prolog && !(b.shader->info.stage == MESA_SHADER_FRAGMENT &&
b.shader->info.fs.uses_sample_shading),
prolog || epilog, cf_base, NULL);
@ -3056,7 +3056,7 @@ agx_launch_precomp(struct agx_batch *batch, struct agx_grid grid,
agx_batch_add_bo(batch, cs->bo);
agx_launch_internal(batch, grid, cs->b.workgroup, cs->b.launch,
PIPE_SHADER_COMPUTE, usc);
MESA_SHADER_COMPUTE, usc);
}
struct asahi_bg_eot
@ -4170,7 +4170,7 @@ agx_launch_gs_prerast(struct agx_batch *batch,
if (xfb_or_queries) {
perf_debug(dev, "Geometry shader transform feedback / query program");
agx_launch(batch, agx_1d(1), agx_workgroup(1, 1, 1), gs->pre_gs, NULL,
PIPE_SHADER_COMPUTE, 0);
MESA_SHADER_COMPUTE, 0);
}
/* Pre-rast geometry shader */
@ -5353,7 +5353,7 @@ agx_launch(struct agx_batch *batch, struct agx_grid grid,
}
#endif
uint32_t usc = agx_build_pipeline(batch, cs, linked, PIPE_SHADER_COMPUTE,
uint32_t usc = agx_build_pipeline(batch, cs, linked, MESA_SHADER_COMPUTE,
variable_shared_mem, subgroups_per_core);
if (cs)
@ -5418,7 +5418,7 @@ agx_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
agx_batch_init_state(batch);
struct agx_uncompiled_shader *uncompiled =
ctx->stage[PIPE_SHADER_COMPUTE].shader;
ctx->stage[MESA_SHADER_COMPUTE].shader;
/* There is exactly one variant, get it */
struct agx_compiled_shader *cs =
@ -5436,7 +5436,7 @@ agx_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
}
}
agx_launch(batch, grid, wg, cs, NULL, PIPE_SHADER_COMPUTE,
agx_launch(batch, grid, wg, cs, NULL, MESA_SHADER_COMPUTE,
info->variable_shared_mem);
/* TODO: Dirty tracking? */

4
src/gallium/drivers/asahi/agx_state.h
View file

@ -98,7 +98,7 @@ static_assert(AGX_SYSVAL_STAGE(MESA_SHADER_GEOMETRY) == AGX_SYSVAL_TABLE_GS,
"fixed enum orderings");
static_assert(AGX_SYSVAL_STAGE(MESA_SHADER_FRAGMENT) == AGX_SYSVAL_TABLE_FS,
"fixed enum orderings");
static_assert(AGX_SYSVAL_STAGE(PIPE_SHADER_COMPUTE) == AGX_SYSVAL_TABLE_CS,
static_assert(AGX_SYSVAL_STAGE(MESA_SHADER_COMPUTE) == AGX_SYSVAL_TABLE_CS,
"fixed enum orderings");
/* Root system value table */
@ -823,7 +823,7 @@ agx_dirty_reset_graphics(struct agx_context *ctx)
ctx->dirty = 0;
for (unsigned i = 0; i < ARRAY_SIZE(ctx->stage); ++i) {
if (i != PIPE_SHADER_COMPUTE)
if (i != MESA_SHADER_COMPUTE)
ctx->stage[i].dirty = 0;
}
}

4
src/gallium/drivers/crocus/crocus_screen.c
View file

@ -139,7 +139,7 @@ crocus_init_shader_caps(struct crocus_screen *screen)
{
const struct intel_device_info *devinfo = &screen->devinfo;
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.shader_caps[i];
@ -181,7 +181,7 @@ crocus_init_shader_caps(struct crocus_screen *screen)
(devinfo->verx10 >= 75) ? CROCUS_MAX_TEXTURE_SAMPLERS : 16;
if (devinfo->ver >= 7 &&
(i == MESA_SHADER_FRAGMENT || i == PIPE_SHADER_COMPUTE))
(i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE))
caps->max_shader_images = CROCUS_MAX_TEXTURE_SAMPLERS;
caps->max_shader_buffers =

12
src/gallium/drivers/d3d12/d3d12_compiler.cpp
View file

@ -734,7 +734,7 @@ d3d12_compare_shader_keys(struct d3d12_selection_context* sel_ctx, const d3d12_s
if (expect->fs.all != have->fs.all)
return false;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
if (memcmp(expect->cs.workgroup_size, have->cs.workgroup_size,
sizeof(have->cs.workgroup_size)))
return false;
@ -811,7 +811,7 @@ d3d12_shader_key_hash(const d3d12_shader_key *key)
case MESA_SHADER_FRAGMENT:
hash += key->fs.all;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
hash = _mesa_hash_data_with_seed(&key->cs, sizeof(key->cs), hash);
break;
case MESA_SHADER_TESS_CTRL:
@ -859,7 +859,7 @@ d3d12_fill_shader_key(struct d3d12_selection_context *sel_ctx,
key->ds.tcs_vertices_out = 0;
key->ds.prev_patch_outputs = 0;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
memset(key->cs.workgroup_size, 0, sizeof(key->cs.workgroup_size));
break;
default: UNREACHABLE("Invalid stage type");
@ -1036,7 +1036,7 @@ d3d12_fill_shader_key(struct d3d12_selection_context *sel_ctx,
key->fs.remap_front_facing = 1;
}
if (stage == PIPE_SHADER_COMPUTE && sel_ctx->variable_workgroup_size) {
if (stage == MESA_SHADER_COMPUTE && sel_ctx->variable_workgroup_size) {
memcpy(key->cs.workgroup_size, sel_ctx->variable_workgroup_size, sizeof(key->cs.workgroup_size));
}
@ -1137,7 +1137,7 @@ select_shader_variant(struct d3d12_selection_context *sel_ctx, d3d12_shader_sele
NIR_PASS(_, new_nir_variant, d3d12_lower_image_casts, &image_format_arr);
}
if (key.stage == PIPE_SHADER_COMPUTE && sel->workgroup_size_variable) {
if (key.stage == MESA_SHADER_COMPUTE && sel->workgroup_size_variable) {
new_nir_variant->info.workgroup_size[0] = static_cast<uint16_t>(key.cs.workgroup_size[0]);
new_nir_variant->info.workgroup_size[1] = static_cast<uint16_t>(key.cs.workgroup_size[1]);
new_nir_variant->info.workgroup_size[2] = static_cast<uint16_t>(key.cs.workgroup_size[2]);
@ -1464,7 +1464,7 @@ d3d12_create_compute_shader(struct d3d12_context *ctx,
const struct pipe_compute_state *shader)
{
struct d3d12_shader_selector *sel = rzalloc(nullptr, d3d12_shader_selector);
sel->stage = PIPE_SHADER_COMPUTE;
sel->stage = MESA_SHADER_COMPUTE;
struct nir_shader *nir = NULL;

12
src/gallium/drivers/d3d12/d3d12_compute_transforms.cpp
View file

@ -486,12 +486,12 @@ d3d12_save_compute_transform_state(struct d3d12_context *ctx, d3d12_compute_tran
memset(save, 0, sizeof(*save));
save->cs = ctx->compute_state;
pipe_resource_reference(&save->cbuf0.buffer, ctx->cbufs[PIPE_SHADER_COMPUTE][1].buffer);
save->cbuf0 = ctx->cbufs[PIPE_SHADER_COMPUTE][1];
pipe_resource_reference(&save->cbuf0.buffer, ctx->cbufs[MESA_SHADER_COMPUTE][1].buffer);
save->cbuf0 = ctx->cbufs[MESA_SHADER_COMPUTE][1];
for (unsigned i = 0; i < ARRAY_SIZE(save->ssbos); ++i) {
pipe_resource_reference(&save->ssbos[i].buffer, ctx->ssbo_views[PIPE_SHADER_COMPUTE][i].buffer);
save->ssbos[i] = ctx->ssbo_views[PIPE_SHADER_COMPUTE][i];
pipe_resource_reference(&save->ssbos[i].buffer, ctx->ssbo_views[MESA_SHADER_COMPUTE][i].buffer);
save->ssbos[i] = ctx->ssbo_views[MESA_SHADER_COMPUTE][i];
}
save->queries_disabled = ctx->queries_disabled;
@ -505,8 +505,8 @@ d3d12_restore_compute_transform_state(struct d3d12_context *ctx, d3d12_compute_t
ctx->base.bind_compute_state(&ctx->base, save->cs);
ctx->base.set_constant_buffer(&ctx->base, PIPE_SHADER_COMPUTE, 1, true, &save->cbuf0);
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, ARRAY_SIZE(save->ssbos), save->ssbos, (1u << ARRAY_SIZE(save->ssbos)) - 1);
ctx->base.set_constant_buffer(&ctx->base, MESA_SHADER_COMPUTE, 1, true, &save->cbuf0);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, ARRAY_SIZE(save->ssbos), save->ssbos, (1u << ARRAY_SIZE(save->ssbos)) - 1);
if (ctx->current_predication)
d3d12_enable_predication(ctx);

6
src/gallium/drivers/d3d12/d3d12_context_graphics.cpp
View file

@ -1839,7 +1839,7 @@ d3d12_disable_fake_so_buffers(struct d3d12_context *ctx)
new_cs_ssbos[1].buffer = target->fill_buffer;
new_cs_ssbos[1].buffer_offset = target->fill_buffer_offset;
new_cs_ssbos[1].buffer_size = target->fill_buffer->width0 - target->fill_buffer_offset;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
pipe_grid_info grid = {};
grid.block[0] = grid.block[1] = grid.block[2] = 1;
@ -1875,13 +1875,13 @@ d3d12_disable_fake_so_buffers(struct d3d12_context *ctx)
new_cs_ssbos[1].buffer = fake_target->base.buffer;
new_cs_ssbos[1].buffer_offset = fake_target->base.buffer_offset;
new_cs_ssbos[1].buffer_size = fake_target->base.buffer_size;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
pipe_constant_buffer cbuf = {};
cbuf.buffer = fake_target->fill_buffer;
cbuf.buffer_offset = fake_target->fill_buffer_offset;
cbuf.buffer_size = fake_target->fill_buffer->width0 - cbuf.buffer_offset;
ctx->base.set_constant_buffer(&ctx->base, PIPE_SHADER_COMPUTE, 1, false, &cbuf);
ctx->base.set_constant_buffer(&ctx->base, MESA_SHADER_COMPUTE, 1, false, &cbuf);
grid.indirect = fake_target->fill_buffer;
grid.indirect_offset = fake_target->fill_buffer_offset + 4;

10
src/gallium/drivers/d3d12/d3d12_draw.cpp
View file

@ -795,7 +795,7 @@ update_draw_indirect_with_sysvals(struct d3d12_context *ctx,
draw_count_cbuf.buffer_offset = indirect_in->indirect_draw_count_offset;
draw_count_cbuf.buffer_size = 4;
draw_count_cbuf.user_buffer = nullptr;
ctx->base.set_constant_buffer(&ctx->base, PIPE_SHADER_COMPUTE, 1, false, &draw_count_cbuf);
ctx->base.set_constant_buffer(&ctx->base, MESA_SHADER_COMPUTE, 1, false, &draw_count_cbuf);
}
pipe_shader_buffer new_cs_ssbos[2];
@ -815,7 +815,7 @@ update_draw_indirect_with_sysvals(struct d3d12_context *ctx,
new_cs_ssbos[1].buffer = ctx->base.screen->resource_create(ctx->base.screen, &output_buf_templ);
new_cs_ssbos[1].buffer_offset = 0;
new_cs_ssbos[1].buffer_size = output_buf_templ.width0;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, 2, new_cs_ssbos, 2);
pipe_grid_info grid = {};
grid.block[0] = grid.block[1] = grid.block[2] = 1;
@ -863,7 +863,7 @@ update_draw_auto(struct d3d12_context *ctx,
new_cs_ssbo.buffer = target->fill_buffer;
new_cs_ssbo.buffer_offset = target->fill_buffer_offset;
new_cs_ssbo.buffer_size = target->fill_buffer->width0 - new_cs_ssbo.buffer_offset;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, 1, &new_cs_ssbo, 1);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, 1, &new_cs_ssbo, 1);
pipe_grid_info grid = {};
grid.block[0] = grid.block[1] = grid.block[2] = 1;
@ -1352,7 +1352,7 @@ d3d12_launch_grid(struct pipe_context *pctx, const struct pipe_grid_info *info)
if (ctx->compute_pipeline_state.root_signature != root_signature) {
ctx->compute_pipeline_state.root_signature = root_signature;
ctx->state_dirty |= D3D12_DIRTY_COMPUTE_ROOT_SIGNATURE;
ctx->shader_dirty[PIPE_SHADER_COMPUTE] |= D3D12_SHADER_DIRTY_ALL;
ctx->shader_dirty[MESA_SHADER_COMPUTE] |= D3D12_SHADER_DIRTY_ALL;
}
}
@ -1414,6 +1414,6 @@ d3d12_launch_grid(struct pipe_context *pctx, const struct pipe_grid_info *info)
ctx->cmdlist_dirty |= D3D12_DIRTY_SHADER;
batch->pending_memory_barrier = false;
ctx->shader_dirty[PIPE_SHADER_COMPUTE] = 0;
ctx->shader_dirty[MESA_SHADER_COMPUTE] = 0;
pipe_resource_reference(&patched_indirect, nullptr);
}

4
src/gallium/drivers/d3d12/d3d12_query.cpp
View file

@ -387,7 +387,7 @@ accumulate_subresult_gpu(struct d3d12_context *ctx, struct d3d12_query *q_parent
new_cs_ssbos[0].buffer = q_parent->subqueries[sub_query].buffer;
new_cs_ssbos[0].buffer_offset = q_parent->subqueries[sub_query].buffer_offset;
new_cs_ssbos[0].buffer_size = q_parent->subqueries[sub_query].query_size * q_parent->subqueries[sub_query].num_queries;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, 1, new_cs_ssbos, 1);
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, 1, new_cs_ssbos, 1);
pipe_grid_info grid = {};
grid.block[0] = grid.block[1] = grid.block[2] = 1;
@ -435,7 +435,7 @@ accumulate_result_gpu(struct d3d12_context *ctx, struct d3d12_query *q,
new_cs_ssbos[num_ssbos].buffer_size = dst->width0;
num_ssbos++;
ctx->base.set_shader_buffers(&ctx->base, PIPE_SHADER_COMPUTE, 0, num_ssbos, new_cs_ssbos, 1 << (num_ssbos - 1));
ctx->base.set_shader_buffers(&ctx->base, MESA_SHADER_COMPUTE, 0, num_ssbos, new_cs_ssbos, 1 << (num_ssbos - 1));
pipe_grid_info grid = {};
grid.block[0] = grid.block[1] = grid.block[2] = 1;

4
src/gallium/drivers/d3d12/d3d12_root_signature.cpp
View file

@ -51,7 +51,7 @@ get_shader_visibility(enum pipe_shader_type stage)
return D3D12_SHADER_VISIBILITY_HULL;
case MESA_SHADER_TESS_EVAL:
return D3D12_SHADER_VISIBILITY_DOMAIN;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return D3D12_SHADER_VISIBILITY_ALL;
default:
UNREACHABLE("unknown shader stage");
@ -122,7 +122,7 @@ create_root_signature(struct d3d12_context *ctx, struct d3d12_root_signature_key
unsigned count = key->compute ? 1 : D3D12_GFX_SHADER_STAGES;
for (unsigned i = 0; i < count; ++i) {
unsigned stage = key->compute ? PIPE_SHADER_COMPUTE : i;
unsigned stage = key->compute ? MESA_SHADER_COMPUTE : i;
D3D12_SHADER_VISIBILITY visibility = get_shader_visibility((enum pipe_shader_type)stage);
if (key->stages[i].end_cb_bindings - key->stages[i].begin_cb_bindings > 0) {

2
src/gallium/drivers/d3d12/d3d12_screen.cpp
View file

@ -127,7 +127,7 @@ d3d12_get_video_mem(struct pipe_screen *pscreen)
static void
d3d12_init_shader_caps(struct d3d12_screen *screen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.shader_caps[i];

2
src/gallium/drivers/freedreno/a4xx/fd4_compute.c
View file

@ -121,7 +121,7 @@ fd4_launch_grid(struct fd_context *ctx,
if (!v)
return;
if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
if (ctx->dirty_shader[MESA_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
cs_program_emit(ring, v);
fd4_emit_cs_state(ctx, ring, v);

12
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View file

@ -913,13 +913,13 @@ void
fd4_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct ir3_shader_variant *cp)
{
enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
unsigned num_textures = ctx->tex[PIPE_SHADER_COMPUTE].num_textures +
enum fd_dirty_shader_state dirty = ctx->dirty_shader[MESA_SHADER_COMPUTE];
unsigned num_textures = ctx->tex[MESA_SHADER_COMPUTE].num_textures +
cp->astc_srgb.count +
cp->tg4.count;
if (dirty & FD_DIRTY_SHADER_TEX) {
emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[PIPE_SHADER_COMPUTE], cp);
emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[MESA_SHADER_COMPUTE], cp);
OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
OUT_RING(ring, 0);
@ -927,13 +927,13 @@ fd4_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
OUT_RING(ring, A4XX_TPL1_TP_FS_TEX_COUNT_CS(
ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ? 0x80 : num_textures));
ctx->shaderimg[MESA_SHADER_COMPUTE].enabled_mask ? 0x80 : num_textures));
if (dirty & FD_DIRTY_SHADER_SSBO)
emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[MESA_SHADER_COMPUTE]);
if (dirty & FD_DIRTY_SHADER_IMAGE)
fd4_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
fd4_emit_images(ctx, ring, MESA_SHADER_COMPUTE, cp);
}
/* emit setup at begin of new cmdstream buffer (don't rely on previous

4
src/gallium/drivers/freedreno/a4xx/fd4_image.c
View file

@ -14,12 +14,12 @@
#include "fd4_texture.h"
static enum a4xx_state_block texsb[] = {
[PIPE_SHADER_COMPUTE] = SB4_CS_TEX,
[MESA_SHADER_COMPUTE] = SB4_CS_TEX,
[MESA_SHADER_FRAGMENT] = SB4_FS_TEX,
};
static enum a4xx_state_block imgsb[] = {
[PIPE_SHADER_COMPUTE] = SB4_CS_SSBO,
[MESA_SHADER_COMPUTE] = SB4_CS_SSBO,
[MESA_SHADER_FRAGMENT] = SB4_SSBO,
};

4
src/gallium/drivers/freedreno/a4xx/fd4_texture.c
View file

@ -228,7 +228,7 @@ fd4_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
sampler_swizzles = fd4_ctx->fsampler_swizzles;
} else if (shader == MESA_SHADER_VERTEX) {
sampler_swizzles = fd4_ctx->vsampler_swizzles;
} else if (shader == PIPE_SHADER_COMPUTE) {
} else if (shader == MESA_SHADER_COMPUTE) {
sampler_swizzles = fd4_ctx->csampler_swizzles;
} else {
assert(0);
@ -278,7 +278,7 @@ fd4_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
fd4_ctx->fastc_srgb = astc_srgb;
} else if (shader == MESA_SHADER_VERTEX) {
fd4_ctx->vastc_srgb = astc_srgb;
} else if (shader == PIPE_SHADER_COMPUTE) {
} else if (shader == MESA_SHADER_COMPUTE) {
fd4_ctx->castc_srgb = astc_srgb;
}
}

2
src/gallium/drivers/freedreno/a5xx/fd5_compute.c
View file

@ -100,7 +100,7 @@ fd5_launch_grid(struct fd_context *ctx,
if (!v)
return;
if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
if (ctx->dirty_shader[MESA_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
cs_program_emit(ctx, ring, v);
fd5_emit_cs_state(ctx, ring, v);

12
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View file

@ -859,12 +859,12 @@ void
fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct ir3_shader_variant *cp)
{
enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
enum fd_dirty_shader_state dirty = ctx->dirty_shader[MESA_SHADER_COMPUTE];
if (dirty & FD_DIRTY_SHADER_TEX) {
bool needs_border = false;
needs_border |=
emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[PIPE_SHADER_COMPUTE]);
emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[MESA_SHADER_COMPUTE]);
if (needs_border)
emit_border_color(ctx, ring);
@ -886,16 +886,16 @@ fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
}
OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask
OUT_RING(ring, ctx->shaderimg[MESA_SHADER_COMPUTE].enabled_mask
? ~0
: ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
: ctx->tex[MESA_SHADER_COMPUTE].num_textures);
if (dirty & FD_DIRTY_SHADER_SSBO)
emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE],
emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[MESA_SHADER_COMPUTE],
cp);
if (dirty & FD_DIRTY_SHADER_IMAGE)
fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
fd5_emit_images(ctx, ring, MESA_SHADER_COMPUTE, cp);
}
/* emit setup at begin of new cmdstream buffer (don't rely on previous

4
src/gallium/drivers/freedreno/a5xx/fd5_image.c
View file

@ -14,12 +14,12 @@
#include "freedreno_resource.h"
static enum a4xx_state_block texsb[] = {
[PIPE_SHADER_COMPUTE] = SB4_CS_TEX,
[MESA_SHADER_COMPUTE] = SB4_CS_TEX,
[MESA_SHADER_FRAGMENT] = SB4_FS_TEX,
};
static enum a4xx_state_block imgsb[] = {
[PIPE_SHADER_COMPUTE] = SB4_CS_SSBO,
[MESA_SHADER_COMPUTE] = SB4_CS_SSBO,
[MESA_SHADER_FRAGMENT] = SB4_SSBO,
};

2
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -527,7 +527,7 @@ fd6_emit_cs_user_consts(struct fd_context *ctx,
struct fd_ringbuffer *ring,
struct fd6_compute_state *cs)
{
emit_user_consts<CHIP>(cs->v, ring, &ctx->constbuf[PIPE_SHADER_COMPUTE]);
emit_user_consts<CHIP>(cs->v, ring, &ctx->constbuf[MESA_SHADER_COMPUTE]);
}
FD_GENX(fd6_emit_cs_user_consts);

4
src/gallium/drivers/freedreno/a6xx/fd6_context.cc
View file

@ -187,7 +187,7 @@ setup_state_map(struct fd_context *ctx)
BIT(FD6_GROUP_GS_TEX));
fd_context_add_shader_map(ctx, MESA_SHADER_FRAGMENT, FD_DIRTY_SHADER_TEX,
BIT(FD6_GROUP_FS_TEX));
fd_context_add_shader_map(ctx, PIPE_SHADER_COMPUTE, FD_DIRTY_SHADER_TEX,
fd_context_add_shader_map(ctx, MESA_SHADER_COMPUTE, FD_DIRTY_SHADER_TEX,
BIT(FD6_GROUP_CS_TEX));
fd_context_add_shader_map(ctx, MESA_SHADER_VERTEX,
@ -209,7 +209,7 @@ setup_state_map(struct fd_context *ctx)
fd_context_add_shader_map(ctx, MESA_SHADER_FRAGMENT,
FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE,
BIT(FD6_GROUP_FS_BINDLESS));
fd_context_add_shader_map(ctx, PIPE_SHADER_COMPUTE,
fd_context_add_shader_map(ctx, MESA_SHADER_COMPUTE,
FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE,
BIT(FD6_GROUP_CS_BINDLESS));
fd_context_add_shader_map(ctx, MESA_SHADER_FRAGMENT,

4
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -770,13 +770,13 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
case FD6_GROUP_CS_TEX:
fd6_state_take_group(
&state,
tex_state(ctx, PIPE_SHADER_COMPUTE),
tex_state(ctx, MESA_SHADER_COMPUTE),
FD6_GROUP_CS_TEX);
break;
case FD6_GROUP_CS_BINDLESS:
fd6_state_take_group(
&state,
fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_COMPUTE, false),
fd6_build_bindless_state<CHIP>(ctx, MESA_SHADER_COMPUTE, false),
FD6_GROUP_CS_BINDLESS);
break;
default:

4
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -126,7 +126,7 @@ descriptor_set(struct fd_context *ctx, enum pipe_shader_type shader)
{
struct fd6_context *fd6_ctx = fd6_context(ctx);
if (shader == PIPE_SHADER_COMPUTE)
if (shader == MESA_SHADER_COMPUTE)
return &fd6_ctx->cs_descriptor_set;
unsigned idx = ir3_shader_descriptor_set(shader);
@ -269,7 +269,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
fd_ringbuffer_attach_bo(ring, set->bo);
if (shader == PIPE_SHADER_COMPUTE) {
if (shader == MESA_SHADER_COMPUTE) {
OUT_REG(ring,
SP_UPDATE_CNTL(
CHIP,

2
src/gallium/drivers/freedreno/a6xx/fd6_texture.cc
View file

@ -645,7 +645,7 @@ build_texture_state(struct fd_context *ctx, enum pipe_shader_type type,
tex_const_reg = REG_A6XX_SP_PS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_PS_TSIZE;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
sb = SB6_CS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
tex_samp_reg = REG_A6XX_SP_CS_SAMPLER_BASE;

14
src/gallium/drivers/freedreno/freedreno_draw.c
View file

@ -558,7 +558,7 @@ fd_launch_grid(struct pipe_context *pctx,
{
struct fd_context *ctx = fd_context(pctx);
const struct fd_shaderbuf_stateobj *so =
&ctx->shaderbuf[PIPE_SHADER_COMPUTE];
&ctx->shaderbuf[MESA_SHADER_COMPUTE];
struct fd_batch *batch, *save_batch = NULL;
if (!fd_render_condition_check(pctx))
@ -577,8 +577,8 @@ fd_launch_grid(struct pipe_context *pctx,
u_foreach_bit (i, so->enabled_mask & ~so->writable_mask)
resource_read(batch, so->sb[i].buffer);
u_foreach_bit (i, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask) {
struct pipe_image_view *img = &ctx->shaderimg[PIPE_SHADER_COMPUTE].si[i];
u_foreach_bit (i, ctx->shaderimg[MESA_SHADER_COMPUTE].enabled_mask) {
struct pipe_image_view *img = &ctx->shaderimg[MESA_SHADER_COMPUTE].si[i];
if (img->access & PIPE_IMAGE_ACCESS_WRITE)
resource_written(batch, img->resource);
else
@ -586,12 +586,12 @@ fd_launch_grid(struct pipe_context *pctx,
}
/* UBO's are read */
u_foreach_bit (i, ctx->constbuf[PIPE_SHADER_COMPUTE].enabled_mask)
resource_read(batch, ctx->constbuf[PIPE_SHADER_COMPUTE].cb[i].buffer);
u_foreach_bit (i, ctx->constbuf[MESA_SHADER_COMPUTE].enabled_mask)
resource_read(batch, ctx->constbuf[MESA_SHADER_COMPUTE].cb[i].buffer);
/* Mark textures as being read */
u_foreach_bit (i, ctx->tex[PIPE_SHADER_COMPUTE].valid_textures)
resource_read(batch, ctx->tex[PIPE_SHADER_COMPUTE].textures[i]->texture);
u_foreach_bit (i, ctx->tex[MESA_SHADER_COMPUTE].valid_textures)
resource_read(batch, ctx->tex[MESA_SHADER_COMPUTE].textures[i]->texture);
/* For global buffers, we don't really know if read or written, so assume
* the worst:

10
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -203,7 +203,7 @@ fd_query_memory_info(struct pipe_screen *pscreen,
static void
fd_init_shader_caps(struct fd_screen *screen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.shader_caps[i];
@ -216,7 +216,7 @@ fd_init_shader_caps(struct fd_screen *screen)
if (screen->info->a6xx.is_a702)
continue;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
if (!has_compute(screen))
continue;
break;
@ -261,7 +261,7 @@ fd_init_shader_caps(struct fd_screen *screen)
caps->int16 =
caps->fp16 =
(is_a5xx(screen) || is_a6xx(screen)) &&
(i == PIPE_SHADER_COMPUTE || i == MESA_SHADER_FRAGMENT) &&
(i == MESA_SHADER_COMPUTE || i == MESA_SHADER_FRAGMENT) &&
!FD_DBG(NOFP16);
caps->glsl_16bit_load_dst = true;
@ -273,7 +273,7 @@ fd_init_shader_caps(struct fd_screen *screen)
/* tgsi_to_nir doesn't support all stages: */
COND(i == MESA_SHADER_VERTEX ||
i == MESA_SHADER_FRAGMENT ||
i == PIPE_SHADER_COMPUTE,
i == MESA_SHADER_COMPUTE,
1 << PIPE_SHADER_IR_TGSI);
if (is_a6xx(screen)) {
@ -302,7 +302,7 @@ fd_init_shader_caps(struct fd_screen *screen)
* but images also need texture state for read access
* (isam/isam.3d)
*/
if (i == MESA_SHADER_FRAGMENT || i == PIPE_SHADER_COMPUTE) {
if (i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE) {
caps->max_shader_buffers =
caps->max_shader_images = 24;
}

2
src/gallium/drivers/freedreno/freedreno_state.c
View file

@ -714,7 +714,7 @@ fd_bind_compute_state(struct pipe_context *pctx, void *state) in_dt
{
struct fd_context *ctx = fd_context(pctx);
ctx->compute = state;
fd_context_dirty_shader(ctx, PIPE_SHADER_COMPUTE, FD_DIRTY_SHADER_PROG);
fd_context_dirty_shader(ctx, MESA_SHADER_COMPUTE, FD_DIRTY_SHADER_PROG);
}
/* used by clover to bind global objects, returning the bo address

2
src/gallium/drivers/freedreno/ir3/ir3_const.h
View file

@ -672,7 +672,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v,
{
assert(gl_shader_stage_is_compute(v->type));
emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
emit_common_consts(v, ring, ctx, MESA_SHADER_COMPUTE);
ir3_emit_cs_driver_params(v, ring, ctx, info);
}

2
src/gallium/drivers/freedreno/ir3/ir3_descriptor.h
View file

@ -40,7 +40,7 @@ ir3_shader_descriptor_set(enum pipe_shader_type shader)
case MESA_SHADER_TESS_EVAL: return 2;
case MESA_SHADER_GEOMETRY: return 3;
case MESA_SHADER_FRAGMENT: return 4;
case PIPE_SHADER_COMPUTE: return 0;
case MESA_SHADER_COMPUTE: return 0;
case MESA_SHADER_KERNEL: return 0;
default:
UNREACHABLE("bad shader stage");

2
src/gallium/drivers/iris/iris_screen.c
View file

@ -201,7 +201,7 @@ iris_get_video_memory(struct iris_screen *screen)
static void
iris_init_shader_caps(struct iris_screen *screen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.shader_caps[i];

2
src/gallium/drivers/llvmpipe/lp_screen.c
View file

@ -128,7 +128,7 @@ llvmpipe_init_shader_caps(struct pipe_screen *screen)
switch (i) {
case MESA_SHADER_FRAGMENT:
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
case PIPE_SHADER_MESH:
case PIPE_SHADER_TASK:
gallivm_init_shader_caps(caps);

22
src/gallium/drivers/llvmpipe/lp_state_cs.c
View file

@ -1457,7 +1457,7 @@ static void
llvmpipe_update_cs(struct llvmpipe_context *lp)
{
struct lp_compute_shader_variant *variant;
variant = llvmpipe_update_cs_variant(lp, PIPE_SHADER_COMPUTE, lp->cs);
variant = llvmpipe_update_cs_variant(lp, MESA_SHADER_COMPUTE, lp->cs);
/* Bind this variant */
lp_cs_ctx_set_cs_variant(lp->csctx, variant);
}
@ -1643,32 +1643,32 @@ llvmpipe_cs_update_derived(struct llvmpipe_context *llvmpipe)
{
if (llvmpipe->cs_dirty & LP_CSNEW_CONSTANTS) {
lp_csctx_set_cs_constants(llvmpipe->csctx,
ARRAY_SIZE(llvmpipe->constants[PIPE_SHADER_COMPUTE]),
llvmpipe->constants[PIPE_SHADER_COMPUTE]);
ARRAY_SIZE(llvmpipe->constants[MESA_SHADER_COMPUTE]),
llvmpipe->constants[MESA_SHADER_COMPUTE]);
update_csctx_consts(llvmpipe, llvmpipe->csctx);
}
if (llvmpipe->cs_dirty & LP_CSNEW_SSBOS) {
lp_csctx_set_cs_ssbos(llvmpipe->csctx,
ARRAY_SIZE(llvmpipe->ssbos[PIPE_SHADER_COMPUTE]),
llvmpipe->ssbos[PIPE_SHADER_COMPUTE]);
ARRAY_SIZE(llvmpipe->ssbos[MESA_SHADER_COMPUTE]),
llvmpipe->ssbos[MESA_SHADER_COMPUTE]);
update_csctx_ssbo(llvmpipe, llvmpipe->csctx);
}
if (llvmpipe->cs_dirty & LP_CSNEW_SAMPLER_VIEW)
lp_csctx_set_sampler_views(llvmpipe->csctx,
llvmpipe->num_sampler_views[PIPE_SHADER_COMPUTE],
llvmpipe->sampler_views[PIPE_SHADER_COMPUTE]);
llvmpipe->num_sampler_views[MESA_SHADER_COMPUTE],
llvmpipe->sampler_views[MESA_SHADER_COMPUTE]);
if (llvmpipe->cs_dirty & LP_CSNEW_SAMPLER)
lp_csctx_set_sampler_state(llvmpipe->csctx,
llvmpipe->num_samplers[PIPE_SHADER_COMPUTE],
llvmpipe->samplers[PIPE_SHADER_COMPUTE]);
llvmpipe->num_samplers[MESA_SHADER_COMPUTE],
llvmpipe->samplers[MESA_SHADER_COMPUTE]);
if (llvmpipe->cs_dirty & LP_CSNEW_IMAGES)
lp_csctx_set_cs_images(llvmpipe->csctx,
ARRAY_SIZE(llvmpipe->images[PIPE_SHADER_COMPUTE]),
llvmpipe->images[PIPE_SHADER_COMPUTE]);
ARRAY_SIZE(llvmpipe->images[MESA_SHADER_COMPUTE]),
llvmpipe->images[MESA_SHADER_COMPUTE]);
if (llvmpipe->cs_dirty & (LP_CSNEW_CS |
LP_CSNEW_IMAGES |

6
src/gallium/drivers/llvmpipe/lp_state_fs.c
View file

@ -4260,7 +4260,7 @@ llvmpipe_set_constant_buffer(struct pipe_context *pipe,
index, data, size);
break;
}
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
llvmpipe->cs_dirty |= LP_CSNEW_CONSTANTS;
break;
case MESA_SHADER_FRAGMENT:
@ -4315,7 +4315,7 @@ llvmpipe_set_shader_buffers(struct pipe_context *pipe,
i, data, size);
break;
}
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
llvmpipe->cs_dirty |= LP_CSNEW_SSBOS;
break;
case PIPE_SHADER_TASK:
@ -4368,7 +4368,7 @@ llvmpipe_set_shader_images(struct pipe_context *pipe,
draw_set_images(llvmpipe->draw, shader, llvmpipe->images[shader],
start_slot + count);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
llvmpipe->cs_dirty |= LP_CSNEW_IMAGES;
break;
case MESA_SHADER_FRAGMENT:

4
src/gallium/drivers/llvmpipe/lp_state_sampler.c
View file

@ -106,7 +106,7 @@ llvmpipe_bind_sampler_states(struct pipe_context *pipe,
llvmpipe->samplers[shader],
llvmpipe->num_samplers[shader]);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
llvmpipe->cs_dirty |= LP_CSNEW_SAMPLER;
break;
case MESA_SHADER_FRAGMENT:
@ -189,7 +189,7 @@ llvmpipe_set_sampler_views(struct pipe_context *pipe,
llvmpipe->sampler_views[shader],
llvmpipe->num_sampler_views[shader]);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
llvmpipe->cs_dirty |= LP_CSNEW_SAMPLER_VIEW;
break;
case MESA_SHADER_FRAGMENT:

2
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
View file

@ -1250,7 +1250,7 @@ nv50_ir_init_prog_info(struct nv50_ir_prog_info *info,
info_out->prop.gp.instanceCount = 1;
info_out->prop.gp.maxVertices = 1;
}
if (info->type == PIPE_SHADER_COMPUTE) {
if (info->type == MESA_SHADER_COMPUTE) {
info->prop.cp.numThreads[0] =
info->prop.cp.numThreads[1] =
info->prop.cp.numThreads[2] = 1;

6
src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
View file

@ -29,7 +29,7 @@ nv50_ir_prog_info_serialize(struct blob *blob, struct nv50_ir_prog_info *info)
nir_serialize(blob, info->bin.nir, true);
if (info->type == PIPE_SHADER_COMPUTE)
if (info->type == MESA_SHADER_COMPUTE)
blob_write_bytes(blob, &info->prop.cp, sizeof(info->prop.cp));
blob_write_bytes(blob, &info->io, sizeof(info->io));
@ -122,7 +122,7 @@ nv50_ir_prog_info_out_serialize(struct blob *blob,
case MESA_SHADER_FRAGMENT:
blob_write_bytes(blob, &info_out->prop.fp, sizeof(info_out->prop.fp));
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
blob_write_bytes(blob, &info_out->prop.cp, sizeof(info_out->prop.cp));
break;
default:
@ -242,7 +242,7 @@ nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset,
case MESA_SHADER_FRAGMENT:
blob_copy_bytes(&reader, &info_out->prop.fp, sizeof(info_out->prop.fp));
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
blob_copy_bytes(&reader, &info_out->prop.cp, sizeof(info_out->prop.cp));
break;
default:

2
src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
View file

@ -176,7 +176,7 @@ public:
virtual void parseDriverInfo(const struct nv50_ir_prog_info *info,
const struct nv50_ir_prog_info_out *info_out) {
if (info_out->type == PIPE_SHADER_COMPUTE) {
if (info_out->type == MESA_SHADER_COMPUTE) {
threads = info->prop.cp.numThreads[0] *
info->prop.cp.numThreads[1] *
info->prop.cp.numThreads[2];

2
src/gallium/drivers/nouveau/nv50/nv50_context.h
View file

@ -250,7 +250,7 @@ nv50_context_shader_stage(unsigned pipe)
case MESA_SHADER_VERTEX: return NV50_SHADER_STAGE_VERTEX;
case MESA_SHADER_FRAGMENT: return NV50_SHADER_STAGE_FRAGMENT;
case MESA_SHADER_GEOMETRY: return NV50_SHADER_STAGE_GEOMETRY;
case PIPE_SHADER_COMPUTE: return NV50_SHADER_STAGE_COMPUTE;
case MESA_SHADER_COMPUTE: return NV50_SHADER_STAGE_COMPUTE;
default:
assert(!"invalid/unhandled shader type");
return 0;

10
src/gallium/drivers/nouveau/nv50/nv50_program.c
View file

@ -262,7 +262,7 @@ nv50_program_assign_varying_slots(struct nv50_ir_prog_info_out *info)
return nv50_vertprog_assign_slots(info);
case MESA_SHADER_FRAGMENT:
return nv50_fragprog_assign_slots(info);
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return 0;
default:
return -1;
@ -370,7 +370,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset,
prog->gp.has_layer = 0;
prog->gp.has_viewport = 0;
if (prog->type == PIPE_SHADER_COMPUTE)
if (prog->type == MESA_SHADER_COMPUTE)
info->prop.cp.inputOffset = 0x14;
info_out.driverPriv = prog;
@ -430,7 +430,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t chipset,
}
prog->gp.vert_count = CLAMP(info_out.prop.gp.maxVertices, 1, 1024);
} else
if (prog->type == PIPE_SHADER_COMPUTE) {
if (prog->type == MESA_SHADER_COMPUTE) {
for (i = 0; i < NV50_MAX_GLOBALS; i++) {
prog->cp.gmem[i] = (struct nv50_gmem_state){
.valid = info_out.prop.cp.gmem[i].valid,
@ -468,7 +468,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
case MESA_SHADER_VERTEX: heap = nv50->screen->vp_code_heap; break;
case MESA_SHADER_GEOMETRY: heap = nv50->screen->gp_code_heap; break;
case MESA_SHADER_FRAGMENT: heap = nv50->screen->fp_code_heap; break;
case PIPE_SHADER_COMPUTE: heap = nv50->screen->fp_code_heap; break;
case MESA_SHADER_COMPUTE: heap = nv50->screen->fp_code_heap; break;
default:
assert(!"invalid program type");
return false;
@ -493,7 +493,7 @@ nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog)
}
}
if (prog->type == PIPE_SHADER_COMPUTE) {
if (prog->type == MESA_SHADER_COMPUTE) {
/* CP code must be uploaded in FP code segment. */
prog_type = NV50_SHADER_STAGE_FRAGMENT;
} else {

2
src/gallium/drivers/nouveau/nv50/nv50_query_hw_sm.c
View file

@ -228,7 +228,7 @@ nv50_hw_sm_end_query(struct nv50_context *nv50, struct nv50_hw_query *hq)
if (unlikely(!screen->pm.prog)) {
struct nv50_program *prog = CALLOC_STRUCT(nv50_program);
prog->type = PIPE_SHADER_COMPUTE;
prog->type = MESA_SHADER_COMPUTE;
prog->translated = true;
prog->max_gpr = 7;
prog->code = (uint32_t *)nv50_read_hw_sm_counters_code;

4
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -104,7 +104,7 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
static void
nv50_init_shader_caps(struct nv50_screen *screen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.base.shader_caps[i];
@ -130,7 +130,7 @@ nv50_init_shader_caps(struct nv50_screen *screen)
/* The chip could handle more sampler views than samplers */
caps->max_sampler_views = MIN2(16, PIPE_MAX_SAMPLERS);
caps->max_shader_buffers =
caps->max_shader_images = i == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
caps->max_shader_images = i == MESA_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
caps->supported_irs = 1 << PIPE_SHADER_IR_NIR;
}
}

4
src/gallium/drivers/nouveau/nv50/nv50_state.c
View file

@ -835,7 +835,7 @@ nv50_cp_state_create(struct pipe_context *pipe,
prog = CALLOC_STRUCT(nv50_program);
if (!prog)
return NULL;
prog->type = PIPE_SHADER_COMPUTE;
prog->type = MESA_SHADER_COMPUTE;
switch(cso->ir_type) {
case PIPE_SHADER_IR_TGSI: {
@ -893,7 +893,7 @@ nv50_set_constant_buffer(struct pipe_context *pipe,
const unsigned s = nv50_context_shader_stage(shader);
const unsigned i = index;
if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
if (unlikely(shader == MESA_SHADER_COMPUTE)) {
if (nv50->constbuf[s][i].user)
nv50->constbuf[s][i].u.buf = NULL;
else

2
src/gallium/drivers/nouveau/nvc0/nvc0_context.h
View file

@ -301,7 +301,7 @@ nvc0_shader_stage(unsigned pipe)
case MESA_SHADER_TESS_EVAL: return 2;
case MESA_SHADER_GEOMETRY: return 3;
case MESA_SHADER_FRAGMENT: return 4;
case PIPE_SHADER_COMPUTE: return 5;
case MESA_SHADER_COMPUTE: return 5;
default:
assert(!"invalid PIPE_SHADER type");
return 0;

14
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
View file

@ -555,7 +555,7 @@ nvc0_program_dump(struct nvc0_program *prog)
{
unsigned pos;
if (prog->type != PIPE_SHADER_COMPUTE) {
if (prog->type != MESA_SHADER_COMPUTE) {
_debug_printf("dumping HDR for type %i\n", prog->type);
for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
_debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
@ -618,7 +618,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
}
if (prog->type == PIPE_SHADER_COMPUTE) {
if (prog->type == MESA_SHADER_COMPUTE) {
if (info->target >= NVISA_GK104_CHIPSET) {
info->io.auxCBSlot = 7;
info->io.msInfoCBSlot = 7;
@ -705,7 +705,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
case MESA_SHADER_FRAGMENT:
ret = nvc0_fp_gen_header(prog, &info_out);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
break;
default:
ret = -1;
@ -762,7 +762,7 @@ static inline int
nvc0_program_alloc_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
{
struct nvc0_screen *screen = nvc0->screen;
const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
const bool is_cp = prog->type == MESA_SHADER_COMPUTE;
int ret;
uint32_t size = prog->code_size;
@ -814,7 +814,7 @@ static inline void
nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog)
{
struct nvc0_screen *screen = nvc0->screen;
const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
const bool is_cp = prog->type == MESA_SHADER_COMPUTE;
uint32_t code_pos = prog->code_base;
uint32_t size_sph = 0;
@ -862,7 +862,7 @@ bool
nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
{
struct nvc0_screen *screen = nvc0->screen;
const bool is_cp = prog->type == PIPE_SHADER_COMPUTE;
const bool is_cp = prog->type == MESA_SHADER_COMPUTE;
int ret;
uint32_t size = prog->code_size;
@ -923,7 +923,7 @@ nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
}
nvc0_program_upload_code(nvc0, progs[i]);
if (progs[i]->type == PIPE_SHADER_COMPUTE) {
if (progs[i]->type == MESA_SHADER_COMPUTE) {
/* Caches have to be invalidated but the CP_START_ID will be
* updated in the launch_grid functions. */
BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(FLUSH), 1);

2
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
View file

@ -2470,7 +2470,7 @@ nvc0_hw_sm_get_program(struct nvc0_screen *screen)
if (!prog)
return NULL;
prog->type = PIPE_SHADER_COMPUTE;
prog->type = MESA_SHADER_COMPUTE;
prog->translated = true;
if (screen->base.class_3d >= GM107_3D_CLASS) {

4
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -116,7 +116,7 @@ nvc0_init_shader_caps(struct nvc0_screen *screen)
{
const uint16_t class_3d = screen->base.class_3d;
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.base.shader_caps[i];
@ -143,7 +143,7 @@ nvc0_init_shader_caps(struct nvc0_screen *screen)
caps->max_shader_images =
class_3d >= NVE4_3D_CLASS ||
i == MESA_SHADER_FRAGMENT ||
i == PIPE_SHADER_COMPUTE ? NVC0_MAX_IMAGES : 0;
i == MESA_SHADER_COMPUTE ? NVC0_MAX_IMAGES : 0;
}
}

4
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View file

@ -724,7 +724,7 @@ nvc0_cp_state_create(struct pipe_context *pipe,
prog = CALLOC_STRUCT(nvc0_program);
if (!prog)
return NULL;
prog->type = PIPE_SHADER_COMPUTE;
prog->type = MESA_SHADER_COMPUTE;
prog->cp.smem_size = cso->static_shared_mem;
@ -797,7 +797,7 @@ nvc0_set_constant_buffer(struct pipe_context *pipe,
const unsigned s = nvc0_shader_stage(shader);
const unsigned i = index;
if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
if (unlikely(shader == MESA_SHADER_COMPUTE)) {
if (nvc0->constbuf[s][i].user)
nvc0->constbuf[s][i].u.buf = NULL;
else

2
src/gallium/drivers/nouveau/nvc0/nve4_compute.c
View file

@ -315,7 +315,7 @@ nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
uint64_t address;
const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
const unsigned s = nvc0_shader_stage(MESA_SHADER_COMPUTE);
unsigned i, n;
uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];

36
src/gallium/drivers/panfrost/pan_cmdstream.c
View file

@ -1615,7 +1615,7 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch,
{
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_compiled_shader *ss = ctx->prog[PIPE_SHADER_COMPUTE];
struct panfrost_compiled_shader *ss = ctx->prog[MESA_SHADER_COMPUTE];
struct pan_ptr t = pan_pool_alloc_desc(&batch->pool.base, LOCAL_STORAGE);
struct pan_compute_dim local_size = {grid->block[0], grid->block[1],
@ -3501,7 +3501,7 @@ panfrost_launch_grid_on_batch(struct pipe_context *pipe,
continue;
struct panfrost_resource *buffer = pan_resource(*res);
panfrost_batch_write_rsrc(batch, buffer, PIPE_SHADER_COMPUTE);
panfrost_batch_write_rsrc(batch, buffer, MESA_SHADER_COMPUTE);
}
if (info->indirect && !PAN_GPU_SUPPORTS_DISPATCH_INDIRECT) {
@ -3528,7 +3528,7 @@ panfrost_launch_grid_on_batch(struct pipe_context *pipe,
/* Conservatively assume workgroup size changes every launch */
ctx->dirty |= PAN_DIRTY_PARAMS;
panfrost_update_shader_state(batch, PIPE_SHADER_COMPUTE);
panfrost_update_shader_state(batch, MESA_SHADER_COMPUTE);
/* We want our compute thread descriptor to be per job.
* Save the global one, and restore it when we're done emitting
@ -3539,7 +3539,7 @@ panfrost_launch_grid_on_batch(struct pipe_context *pipe,
/* if indirect, mark the indirect buffer as being read */
if (info->indirect)
panfrost_batch_read_rsrc(batch, pan_resource(info->indirect), PIPE_SHADER_COMPUTE);
panfrost_batch_read_rsrc(batch, pan_resource(info->indirect), MESA_SHADER_COMPUTE);
/* launch it */
JOBX(launch_grid)(batch, info);
@ -3583,17 +3583,17 @@ panfrost_launch_afbc_conv_shader(struct panfrost_batch *batch, void *cso,
};
struct panfrost_constant_buffer *pbuf =
&batch->ctx->constant_buffer[PIPE_SHADER_COMPUTE];
saved_cso = batch->ctx->uncompiled[PIPE_SHADER_COMPUTE];
&batch->ctx->constant_buffer[MESA_SHADER_COMPUTE];
saved_cso = batch->ctx->uncompiled[MESA_SHADER_COMPUTE];
util_copy_constant_buffer(&pbuf->cb[0], &saved_const, true);
pctx->bind_compute_state(pctx, cso);
pctx->set_constant_buffer(pctx, PIPE_SHADER_COMPUTE, 0, false, cbuf);
pctx->set_constant_buffer(pctx, MESA_SHADER_COMPUTE, 0, false, cbuf);
panfrost_launch_grid_on_batch(pctx, batch, &grid);
pctx->bind_compute_state(pctx, saved_cso);
pctx->set_constant_buffer(pctx, PIPE_SHADER_COMPUTE, 0, true, &saved_const);
pctx->set_constant_buffer(pctx, MESA_SHADER_COMPUTE, 0, true, &saved_const);
}
#define LAUNCH_AFBC_CONV_SHADER(name, batch, rsrc, consts, nr_blocks) \
@ -3625,8 +3625,8 @@ panfrost_afbc_size(struct panfrost_batch *batch, struct panfrost_resource *src,
src->image.props.modifier,
u_minify(src->image.props.extent_px.height, level));
panfrost_batch_read_rsrc(batch, src, PIPE_SHADER_COMPUTE);
panfrost_batch_write_bo(batch, layout, PIPE_SHADER_COMPUTE);
panfrost_batch_read_rsrc(batch, src, MESA_SHADER_COMPUTE);
panfrost_batch_write_bo(batch, layout, MESA_SHADER_COMPUTE);
LAUNCH_AFBC_CONV_SHADER(size, batch, src, consts, nr_sblocks);
}
@ -3661,9 +3661,9 @@ panfrost_afbc_pack(struct panfrost_batch *batch, struct panfrost_resource *src,
.dst_stride = dst_stride_sb,
};
panfrost_batch_read_rsrc(batch, src, PIPE_SHADER_COMPUTE);
panfrost_batch_write_bo(batch, dst, PIPE_SHADER_COMPUTE);
panfrost_batch_add_bo(batch, layout, PIPE_SHADER_COMPUTE);
panfrost_batch_read_rsrc(batch, src, MESA_SHADER_COMPUTE);
panfrost_batch_write_bo(batch, dst, MESA_SHADER_COMPUTE);
panfrost_batch_add_bo(batch, layout, MESA_SHADER_COMPUTE);
LAUNCH_AFBC_CONV_SHADER(pack, batch, src, consts, nr_sblocks);
}
@ -3766,7 +3766,7 @@ panfrost_mtk_detile_compute(struct panfrost_context *ctx, struct pipe_blit_info
panfrost_flush_all_batches(ctx, "mtk_detile pre-barrier");
struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
pipe->set_shader_images(pipe, PIPE_SHADER_COMPUTE, 0, 4, 0, image);
pipe->set_shader_images(pipe, MESA_SHADER_COMPUTE, 0, 4, 0, image);
/* launch the compute shader */
struct pan_mod_convert_shader_data *shader =
@ -3789,18 +3789,18 @@ panfrost_mtk_detile_compute(struct panfrost_context *ctx, struct pipe_blit_info
struct pipe_constant_buffer saved_const = {};
struct panfrost_constant_buffer *pbuf =
&batch->ctx->constant_buffer[PIPE_SHADER_COMPUTE];
void *saved_cso = batch->ctx->uncompiled[PIPE_SHADER_COMPUTE];
&batch->ctx->constant_buffer[MESA_SHADER_COMPUTE];
void *saved_cso = batch->ctx->uncompiled[MESA_SHADER_COMPUTE];
void *cso = shader->mtk_tiled.detile_cso;
util_copy_constant_buffer(&pbuf->cb[0], &saved_const, true);
pipe->bind_compute_state(pipe, cso);
pipe->set_constant_buffer(pipe, PIPE_SHADER_COMPUTE, 0, false, &cbuf);
pipe->set_constant_buffer(pipe, MESA_SHADER_COMPUTE, 0, false, &cbuf);
panfrost_launch_grid_on_batch(pipe, batch, &grid_info);
pipe->bind_compute_state(pipe, saved_cso);
pipe->set_constant_buffer(pipe, PIPE_SHADER_COMPUTE, 0, true, &saved_const);
pipe->set_constant_buffer(pipe, MESA_SHADER_COMPUTE, 0, true, &saved_const);
panfrost_resource_restore_format(pan_resource(y_src), &y_src_save);
panfrost_resource_restore_format(pan_resource(uv_src), &uv_src_save);

2
src/gallium/drivers/panfrost/pan_context.h
View file

@ -551,7 +551,7 @@ panfrost_clean_state_3d(struct panfrost_context *ctx)
ctx->dirty = 0;
for (unsigned i = 0; i < PIPE_SHADER_TYPES; ++i) {
if (i != PIPE_SHADER_COMPUTE)
if (i != MESA_SHADER_COMPUTE)
ctx->dirty_shader[i] = 0;
}
}

10
src/gallium/drivers/panfrost/pan_csf.c
View file

@ -906,7 +906,7 @@ csf_emit_shader_regs(struct panfrost_batch *batch, enum pipe_shader_type stage,
uint64_t resources = panfrost_emit_resources(batch, stage);
assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_FRAGMENT ||
stage == PIPE_SHADER_COMPUTE);
stage == MESA_SHADER_COMPUTE);
#if PAN_ARCH >= 12
unsigned offset = (stage == MESA_SHADER_FRAGMENT) ? 2 : 0;
@ -928,16 +928,16 @@ GENX(csf_launch_grid)(struct panfrost_batch *batch,
const struct pipe_grid_info *info)
{
/* Empty compute programs are invalid and don't make sense */
if (batch->rsd[PIPE_SHADER_COMPUTE] == 0)
if (batch->rsd[MESA_SHADER_COMPUTE] == 0)
return;
struct panfrost_context *ctx = batch->ctx;
struct panfrost_device *dev = pan_device(ctx->base.screen);
struct panfrost_compiled_shader *cs = ctx->prog[PIPE_SHADER_COMPUTE];
struct panfrost_compiled_shader *cs = ctx->prog[MESA_SHADER_COMPUTE];
struct cs_builder *b = batch->csf.cs.builder;
csf_emit_shader_regs(batch, PIPE_SHADER_COMPUTE,
batch->rsd[PIPE_SHADER_COMPUTE]);
csf_emit_shader_regs(batch, MESA_SHADER_COMPUTE,
batch->rsd[MESA_SHADER_COMPUTE]);
cs_move64_to(b, cs_sr_reg64(b, COMPUTE, TSD_0), batch->tls.gpu);

20
src/gallium/drivers/panfrost/pan_jm.c
View file

@ -330,14 +330,14 @@ GENX(jm_launch_grid)(struct panfrost_batch *batch,
}
pan_section_pack(t.cpu, COMPUTE_JOB, DRAW, cfg) {
cfg.state = batch->rsd[PIPE_SHADER_COMPUTE];
cfg.attributes = batch->attribs[PIPE_SHADER_COMPUTE];
cfg.attribute_buffers = batch->attrib_bufs[PIPE_SHADER_COMPUTE];
cfg.state = batch->rsd[MESA_SHADER_COMPUTE];
cfg.attributes = batch->attribs[MESA_SHADER_COMPUTE];
cfg.attribute_buffers = batch->attrib_bufs[MESA_SHADER_COMPUTE];
cfg.thread_storage = batch->tls.gpu;
cfg.uniform_buffers = batch->uniform_buffers[PIPE_SHADER_COMPUTE];
cfg.push_uniforms = batch->push_uniforms[PIPE_SHADER_COMPUTE];
cfg.textures = batch->textures[PIPE_SHADER_COMPUTE];
cfg.samplers = batch->samplers[PIPE_SHADER_COMPUTE];
cfg.uniform_buffers = batch->uniform_buffers[MESA_SHADER_COMPUTE];
cfg.push_uniforms = batch->push_uniforms[MESA_SHADER_COMPUTE];
cfg.textures = batch->textures[MESA_SHADER_COMPUTE];
cfg.samplers = batch->samplers[MESA_SHADER_COMPUTE];
}
#if PAN_ARCH == 4
@ -346,7 +346,7 @@ GENX(jm_launch_grid)(struct panfrost_batch *batch,
#endif
#else
struct panfrost_context *ctx = batch->ctx;
struct panfrost_compiled_shader *cs = ctx->prog[PIPE_SHADER_COMPUTE];
struct panfrost_compiled_shader *cs = ctx->prog[MESA_SHADER_COMPUTE];
pan_section_pack(t.cpu, COMPUTE_JOB, PAYLOAD, cfg) {
cfg.workgroup_size_x = info->block[0];
@ -357,8 +357,8 @@ GENX(jm_launch_grid)(struct panfrost_batch *batch,
cfg.workgroup_count_y = num_wg[1];
cfg.workgroup_count_z = num_wg[2];
jm_emit_shader_env(batch, &cfg.compute, PIPE_SHADER_COMPUTE,
batch->rsd[PIPE_SHADER_COMPUTE]);
jm_emit_shader_env(batch, &cfg.compute, MESA_SHADER_COMPUTE,
batch->rsd[MESA_SHADER_COMPUTE]);
/* Workgroups may be merged if the shader does not use barriers
* or shared memory. This condition is checked against the

4
src/gallium/drivers/panfrost/pan_screen.c
View file

@ -489,14 +489,14 @@ panfrost_init_shader_caps(struct panfrost_screen *screen)
struct panfrost_device *dev = &screen->dev;
bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&screen->base.shader_caps[i];
switch (i) {
case MESA_SHADER_VERTEX:
case MESA_SHADER_FRAGMENT:
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
break;
default:
continue;

6
src/gallium/drivers/panfrost/pan_shader.c
View file

@ -406,7 +406,7 @@ panfrost_update_shader_variant(struct panfrost_context *ctx,
enum pipe_shader_type type)
{
/* No shader variants for compute */
if (type == PIPE_SHADER_COMPUTE)
if (type == MESA_SHADER_COMPUTE)
return;
/* We need linking information, defer this */
@ -610,9 +610,9 @@ panfrost_bind_compute_state(struct pipe_context *pipe, void *cso)
struct panfrost_context *ctx = pan_context(pipe);
struct panfrost_uncompiled_shader *uncompiled = cso;
ctx->uncompiled[PIPE_SHADER_COMPUTE] = uncompiled;
ctx->uncompiled[MESA_SHADER_COMPUTE] = uncompiled;
ctx->prog[PIPE_SHADER_COMPUTE] =
ctx->prog[MESA_SHADER_COMPUTE] =
uncompiled ? util_dynarray_begin(&uncompiled->variants) : NULL;
}

14
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -146,7 +146,7 @@ static void evergreen_cs_set_constant_buffer(struct r600_context *rctx,
cb.buffer = buffer;
cb.user_buffer = NULL;
rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_COMPUTE, cb_index, false, &cb);
rctx->b.b.set_constant_buffer(&rctx->b.b, MESA_SHADER_COMPUTE, cb_index, false, &cb);
}
/* We need to define these R600 registers here, because we can't include
@ -169,7 +169,7 @@ static void *evergreen_create_compute_state(struct pipe_context *ctx,
shader->ctx = rctx;
shader->local_size = cso->static_shared_mem;
shader->sel = r600_create_shader_state_tokens(ctx, cso->prog, cso->ir_type, PIPE_SHADER_COMPUTE);
shader->sel = r600_create_shader_state_tokens(ctx, cso->prog, cso->ir_type, MESA_SHADER_COMPUTE);
/* Precompile the shader with the expected shader key, to reduce jank at
* draw time. Also produces output for shader-db.
@ -336,7 +336,7 @@ static void compute_emit_cs(struct r600_context *rctx,
rctx->cs_block_grid_sizes[i + 4] = info->indirect ? indirect_grid[i] : info->grid[i];
}
rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0;
rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
rctx->driver_consts[MESA_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
if (rctx->b.gfx_level == CAYMAN)
global_atomic_count = cayman_emit_atomic_buffer_setup_count(rctx, current, combined_atomics, global_atomic_count);
@ -346,7 +346,7 @@ static void compute_emit_cs(struct r600_context *rctx,
r600_need_cs_space(rctx, 0, true, global_atomic_count);
if (need_buf_const) {
eg_setup_buffer_constants(rctx, PIPE_SHADER_COMPUTE);
eg_setup_buffer_constants(rctx, MESA_SHADER_COMPUTE);
}
r600_update_driver_const_buffers(rctx, true);
@ -384,13 +384,13 @@ static void compute_emit_cs(struct r600_context *rctx,
r600_emit_atom(rctx, &rctx->b.render_cond_atom);
/* Emit constant buffer state */
r600_emit_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
r600_emit_atom(rctx, &rctx->constbuf_state[MESA_SHADER_COMPUTE].atom);
/* Emit sampler state */
r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
r600_emit_atom(rctx, &rctx->samplers[MESA_SHADER_COMPUTE].states.atom);
/* Emit sampler view (texture resource) state */
r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
r600_emit_atom(rctx, &rctx->samplers[MESA_SHADER_COMPUTE].views.atom);
/* Emit images state */
r600_emit_atom(rctx, &rctx->compute_images.atom);

28
src/gallium/drivers/r600/evergreen_state.c
View file

@ -2387,7 +2387,7 @@ static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct
static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[MESA_SHADER_COMPUTE],
EG_FETCH_CONSTANTS_OFFSET_CS,
R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0,
R_028F40_ALU_CONST_CACHE_LS_0,
@ -2513,7 +2513,7 @@ static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r6
static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
evergreen_emit_sampler_views(rctx, &rctx->samplers[MESA_SHADER_COMPUTE].views,
EG_FETCH_CONSTANTS_OFFSET_CS + R600_MAX_CONST_BUFFERS, RADEON_CP_PACKET3_COMPUTE_MODE);
}
@ -2882,7 +2882,7 @@ static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r
static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
evergreen_emit_sampler_states(rctx, &rctx->samplers[MESA_SHADER_COMPUTE], 90,
R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
RADEON_CP_PACKET3_COMPUTE_MODE);
}
@ -4438,12 +4438,12 @@ static void evergreen_set_shader_buffers(struct pipe_context *ctx,
unsigned old_mask;
if ((shader != MESA_SHADER_FRAGMENT &&
shader != PIPE_SHADER_COMPUTE) || count == 0)
shader != MESA_SHADER_COMPUTE) || count == 0)
return;
if (shader == MESA_SHADER_FRAGMENT)
istate = &rctx->fragment_buffers;
else if (shader == PIPE_SHADER_COMPUTE)
else if (shader == MESA_SHADER_COMPUTE)
istate = &rctx->compute_buffers;
old_mask = istate->enabled_mask;
@ -4539,17 +4539,17 @@ static void evergreen_set_shader_images(struct pipe_context *ctx,
unsigned old_mask;
struct r600_image_state *istate = NULL;
int idx;
if (shader != MESA_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_FRAGMENT && shader != MESA_SHADER_COMPUTE)
return;
if (!count && !unbind_num_trailing_slots)
return;
if (shader == MESA_SHADER_FRAGMENT)
istate = &rctx->fragment_images;
else if (shader == PIPE_SHADER_COMPUTE)
else if (shader == MESA_SHADER_COMPUTE)
istate = &rctx->compute_images;
assert (shader == MESA_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
assert (shader == MESA_SHADER_FRAGMENT || shader == MESA_SHADER_COMPUTE);
old_mask = istate->enabled_mask;
for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
@ -4756,7 +4756,7 @@ static void evergreen_get_shader_buffers(struct r600_context *rctx,
uint start_slot, uint count,
struct pipe_shader_buffer *sbuf)
{
assert(shader == PIPE_SHADER_COMPUTE);
assert(shader == MESA_SHADER_COMPUTE);
int idx, i;
struct r600_image_state *istate = &rctx->compute_buffers;
struct r600_image_view *rview;
@ -4789,9 +4789,9 @@ static void evergreen_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_s
st->saved_compute = rctx->cs_shader_state.shader;
/* save constant buffer 0 */
evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
evergreen_get_pipe_constant_buffer(rctx, MESA_SHADER_COMPUTE, 0, &st->saved_const0);
/* save ssbo 0 */
evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
evergreen_get_shader_buffers(rctx, MESA_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
}
@ -4823,7 +4823,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->constbuf_state[MESA_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[MESA_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[MESA_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
r600_init_atom(rctx, &rctx->constbuf_state[MESA_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
/* shader program */
r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
/* sampler */
@ -4832,7 +4832,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
/* resources */
r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
@ -4841,7 +4841,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[MESA_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);

8
src/gallium/drivers/r600/r600_pipe.c
View file

@ -273,14 +273,14 @@ fail:
static void r600_init_shader_caps(struct r600_screen *rscreen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&rscreen->b.b.shader_caps[i];
switch (i) {
case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
if (rscreen->b.family < CHIP_CEDAR)
continue;
break;
@ -297,7 +297,7 @@ static void r600_init_shader_caps(struct r600_screen *rscreen)
caps->max_outputs = i == MESA_SHADER_FRAGMENT ? 8 : 32;
caps->max_temps = 256; /* Max native temporaries. */
caps->max_const_buffer0_size = i == PIPE_SHADER_COMPUTE ?
caps->max_const_buffer0_size = i == MESA_SHADER_COMPUTE ?
MIN2(rscreen->b.b.compute_caps.max_mem_alloc_size, INT_MAX) :
R600_MAX_CONST_BUFFER_SIZE;
@ -316,7 +316,7 @@ static void r600_init_shader_caps(struct r600_screen *rscreen)
caps->max_shader_buffers =
caps->max_shader_images =
rscreen->b.family >= CHIP_CEDAR &&
(i == MESA_SHADER_FRAGMENT || i == PIPE_SHADER_COMPUTE) ? 8 : 0;
(i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE) ? 8 : 0;
if (rscreen->b.family >= CHIP_CEDAR &&
rscreen->has_atomics) {

2
src/gallium/drivers/r600/r600_pipe_common.h
View file

@ -53,7 +53,7 @@ struct u_log_context;
#define DBG_GS (1 << MESA_SHADER_GEOMETRY)
#define DBG_TCS (1 << MESA_SHADER_TESS_CTRL)
#define DBG_TES (1 << MESA_SHADER_TESS_EVAL)
#define DBG_CS (1 << PIPE_SHADER_COMPUTE)
#define DBG_CS (1 << MESA_SHADER_COMPUTE)
#define DBG_ALL_SHADERS (DBG_FS - 1)
#define DBG_FS (1 << 6) /* fetch shader */
#define DBG_TEX (1 << 7)

8
src/gallium/drivers/r600/r600_query.c
View file

@ -1579,8 +1579,8 @@ static void r600_restore_qbo_state(struct r600_common_context *rctx,
struct r600_qbo_state *st)
{
rctx->b.bind_compute_state(&rctx->b, st->saved_compute);
rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo, ~0);
rctx->b.set_constant_buffer(&rctx->b, MESA_SHADER_COMPUTE, 0, true, &st->saved_const0);
rctx->b.set_shader_buffers(&rctx->b, MESA_SHADER_COMPUTE, 0, 3, st->saved_ssbo, ~0);
for (unsigned i = 0; i < 3; ++i)
pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
}
@ -1712,9 +1712,9 @@ static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
} else
consts.buffer_offset = 0;
rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, false, &constant_buffer);
rctx->b.set_constant_buffer(&rctx->b, MESA_SHADER_COMPUTE, 0, false, &constant_buffer);
rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo, ~0);
rctx->b.set_shader_buffers(&rctx->b, MESA_SHADER_COMPUTE, 0, 3, ssbo, ~0);
if ((flags & PIPE_QUERY_WAIT) && qbuf == &query->buffer) {
uint64_t va;

2
src/gallium/drivers/r600/r600_shader.c
View file

@ -268,7 +268,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
r600_update_ps_state(ctx, shader);
}
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
evergreen_update_ls_state(ctx, shader);
break;
default:

20
src/gallium/drivers/r600/r600_state_common.c
View file

@ -746,7 +746,7 @@ static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
int value = 0;
switch (shader) {
case MESA_SHADER_FRAGMENT:
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
default:
break;
case MESA_SHADER_VERTEX:
@ -840,7 +840,7 @@ static inline void r600_shader_selector_key(const struct pipe_context *ctx,
key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, MESA_SHADER_TESS_CTRL);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
break;
default:
assert(0);
@ -881,7 +881,7 @@ r600_shader_precompile_key(const struct pipe_context *ctx,
key->tcs.prim_mode = MESA_PRIM_TRIANGLES;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
break;
default:
@ -1323,8 +1323,8 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
struct pipe_constant_buffer cb;
int start, end;
start = compute_only ? PIPE_SHADER_COMPUTE : 0;
end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
start = compute_only ? MESA_SHADER_COMPUTE : 0;
end = compute_only ? PIPE_SHADER_TYPES : MESA_SHADER_COMPUTE;
int last_vertex_stage = MESA_SHADER_VERTEX;
if (rctx->tes_shader)
@ -1368,7 +1368,7 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
}
else if (info->cs_block_grid_size_dirty) {
assert(sh == PIPE_SHADER_COMPUTE);
assert(sh == MESA_SHADER_COMPUTE);
if (!size) {
ptr = rctx->cs_block_grid_sizes;
size = R600_CS_BLOCK_GRID_SIZE;
@ -1399,7 +1399,7 @@ void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_on
memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
if (sh == MESA_SHADER_FRAGMENT)
memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
if (sh == PIPE_SHADER_COMPUTE)
if (sh == MESA_SHADER_COMPUTE)
memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
if (sh == MESA_SHADER_TESS_CTRL)
memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
@ -1497,7 +1497,7 @@ void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
if (shader_type == MESA_SHADER_FRAGMENT) {
images = &rctx->fragment_images;
} else if (shader_type == PIPE_SHADER_COMPUTE) {
} else if (shader_type == MESA_SHADER_COMPUTE) {
images = &rctx->compute_images;
}
@ -1673,7 +1673,7 @@ void r600_update_compressed_resource_state(struct r600_context *rctx, bool compu
rctx->b.last_compressed_colortex_counter = counter;
if (compute_only) {
r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
r600_update_compressed_colortex_mask(&rctx->samplers[MESA_SHADER_COMPUTE].views);
} else {
for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
@ -1689,7 +1689,7 @@ void r600_update_compressed_resource_state(struct r600_context *rctx, bool compu
struct r600_samplerview_state *views = &rctx->samplers[i].views;
if (compute_only)
if (i != PIPE_SHADER_COMPUTE)
if (i != MESA_SHADER_COMPUTE)
continue;
if (views->compressed_depthtex_mask) {
r600_decompress_depth_textures(rctx, views);

2
src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp
View file

@ -59,7 +59,7 @@ ComputeShader::process_stage_intrinsic(nir_intrinsic_instr *instr)
void
ComputeShader::do_get_shader_info(r600_shader *sh_info)
{
sh_info->processor_type = PIPE_SHADER_COMPUTE;
sh_info->processor_type = MESA_SHADER_COMPUTE;
}
bool

2
src/gallium/drivers/radeonsi/gfx11_query.c
View file

@ -374,7 +374,7 @@ static void gfx11_sh_query_get_result_resource(struct si_context *sctx, struct s
ssbo[2].buffer_size = is_result_64bit ? 8 : 4;
}
sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, false, &constant_buffer);
sctx->b.set_constant_buffer(&sctx->b, MESA_SHADER_COMPUTE, 0, false, &constant_buffer);
if (flags & PIPE_QUERY_WAIT) {
uint64_t va;

8
src/gallium/drivers/radeonsi/si_barrier.c
View file

@ -513,10 +513,10 @@ void si_barrier_before_internal_op(struct si_context *sctx, unsigned flags,
SI_BIND_SHADER_BUFFER(MESA_SHADER_FRAGMENT) |
SI_BIND_IMAGE_BUFFER(MESA_SHADER_FRAGMENT) |
SI_BIND_SAMPLER_BUFFER(MESA_SHADER_FRAGMENT);
const unsigned cs_mask = SI_BIND_CONSTANT_BUFFER(PIPE_SHADER_COMPUTE) |
SI_BIND_SHADER_BUFFER(PIPE_SHADER_COMPUTE) |
SI_BIND_IMAGE_BUFFER(PIPE_SHADER_COMPUTE) |
SI_BIND_SAMPLER_BUFFER(PIPE_SHADER_COMPUTE);
const unsigned cs_mask = SI_BIND_CONSTANT_BUFFER(MESA_SHADER_COMPUTE) |
SI_BIND_SHADER_BUFFER(MESA_SHADER_COMPUTE) |
SI_BIND_IMAGE_BUFFER(MESA_SHADER_COMPUTE) |
SI_BIND_SAMPLER_BUFFER(MESA_SHADER_COMPUTE);
for (unsigned i = 0; i < num_buffers; i++) {
struct si_resource *buf = si_resource(buffers[i].buffer);

18
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -164,9 +164,9 @@ static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe
sel->screen = sscreen;
simple_mtx_init(&sel->mutex, mtx_plain);
sel->const_and_shader_buf_descriptors_index =
si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);
si_const_and_shader_buffer_descriptors_idx(MESA_SHADER_COMPUTE);
sel->sampler_and_images_descriptors_index =
si_sampler_and_image_descriptors_idx(PIPE_SHADER_COMPUTE);
si_sampler_and_image_descriptors_idx(MESA_SHADER_COMPUTE);
sel->info.base.shared_size = cso->static_shared_mem;
program->shader.selector = &program->sel;
@ -220,7 +220,7 @@ static void si_bind_compute_state(struct pipe_context *ctx, void *state)
/* Wait because we need active slot usage masks. */
util_queue_fence_wait(&sel->ready);
si_update_common_shader_state(sctx, sel, PIPE_SHADER_COMPUTE);
si_update_common_shader_state(sctx, sel, MESA_SHADER_COMPUTE);
sctx->compute_shaderbuf_sgprs_dirty = true;
sctx->compute_image_sgprs_dirty = true;
@ -842,7 +842,7 @@ static bool si_check_needs_implicit_sync(struct si_context *sctx, uint32_t usage
* TODO: Bindless textures are not handled, and thus are not synchronized.
*/
struct si_shader_info *info = &sctx->cs_shader_state.program->sel.info;
struct si_samplers *samplers = &sctx->samplers[PIPE_SHADER_COMPUTE];
struct si_samplers *samplers = &sctx->samplers[MESA_SHADER_COMPUTE];
unsigned mask = samplers->enabled_mask & info->base.textures_used;
while (mask) {
@ -854,7 +854,7 @@ static bool si_check_needs_implicit_sync(struct si_context *sctx, uint32_t usage
return true;
}
struct si_images *images = &sctx->images[PIPE_SHADER_COMPUTE];
struct si_images *images = &sctx->images[MESA_SHADER_COMPUTE];
mask = BITFIELD_MASK(info->base.num_images) & images->enabled_mask;
while (mask) {
@ -907,9 +907,9 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
}
if (sctx->gfx_level < GFX11)
gfx6_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
gfx6_decompress_textures(sctx, 1 << MESA_SHADER_COMPUTE);
else if (sctx->gfx_level < GFX12)
gfx11_decompress_textures(sctx, 1 << PIPE_SHADER_COMPUTE);
gfx11_decompress_textures(sctx, 1 << MESA_SHADER_COMPUTE);
}
if (info->indirect) {
@ -996,11 +996,11 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
if (sctx->gfx_level < GFX12) {
/* Mark displayable DCC as dirty for bound images. */
unsigned display_dcc_store_mask = sctx->images[PIPE_SHADER_COMPUTE].display_dcc_store_mask &
unsigned display_dcc_store_mask = sctx->images[MESA_SHADER_COMPUTE].display_dcc_store_mask &
BITFIELD_MASK(program->sel.info.base.num_images);
while (display_dcc_store_mask) {
struct si_texture *tex = (struct si_texture *)
sctx->images[PIPE_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
sctx->images[MESA_SHADER_COMPUTE].views[u_bit_scan(&display_dcc_store_mask)].resource;
si_mark_display_dcc_dirty(sctx, tex);
}

20
src/gallium/drivers/radeonsi/si_compute_blit.c
View file

@ -62,17 +62,17 @@ void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_inf
/* Save states. */
struct pipe_shader_buffer saved_sb[3] = {};
assert(num_buffers <= ARRAY_SIZE(saved_sb));
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, num_buffers, saved_sb);
si_get_shader_buffers(sctx, MESA_SHADER_COMPUTE, 0, num_buffers, saved_sb);
unsigned saved_writable_mask = 0;
for (unsigned i = 0; i < num_buffers; i++) {
if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
if (sctx->const_and_shader_buffers[MESA_SHADER_COMPUTE].writable_mask &
(1u << si_get_shaderbuf_slot(i)))
saved_writable_mask |= 1 << i;
}
/* Bind buffers and launch compute. */
si_set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_buffers, buffers,
si_set_shader_buffers(&sctx->b, MESA_SHADER_COMPUTE, 0, num_buffers, buffers,
writeable_bitmask,
true /* don't update bind_history to prevent unnecessary syncs later */);
@ -81,7 +81,7 @@ void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_inf
si_compute_end_internal(sctx);
/* Restore states. */
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_buffers, saved_sb,
sctx->b.set_shader_buffers(&sctx->b, MESA_SHADER_COMPUTE, 0, num_buffers, saved_sb,
saved_writable_mask);
for (int i = 0; i < num_buffers; i++)
pipe_resource_reference(&saved_sb[i].buffer, NULL);
@ -323,19 +323,19 @@ static void si_compute_save_and_bind_images(struct si_context *sctx, unsigned nu
}
/* Save the image. */
util_copy_image_view(&saved_images[i], &sctx->images[PIPE_SHADER_COMPUTE].views[i]);
util_copy_image_view(&saved_images[i], &sctx->images[MESA_SHADER_COMPUTE].views[i]);
}
/* This must be before the barrier and si_compute_begin_internal because it might invoke DCC
* decompression.
*/
sctx->b.set_shader_images(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_images, 0, images);
sctx->b.set_shader_images(&sctx->b, MESA_SHADER_COMPUTE, 0, num_images, 0, images);
}
static void si_compute_restore_images(struct si_context *sctx, unsigned num_images,
struct pipe_image_view *saved_images)
{
sctx->b.set_shader_images(&sctx->b, PIPE_SHADER_COMPUTE, 0, num_images, 0, saved_images);
sctx->b.set_shader_images(&sctx->b, MESA_SHADER_COMPUTE, 0, num_images, 0, saved_images);
for (unsigned i = 0; i < num_images; i++)
pipe_resource_reference(&saved_images[i].resource, NULL);
}
@ -449,7 +449,7 @@ void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex
/* Save states. */
struct pipe_image_view saved_image = {0};
util_copy_image_view(&saved_image, &sctx->images[PIPE_SHADER_COMPUTE].views[0]);
util_copy_image_view(&saved_image, &sctx->images[MESA_SHADER_COMPUTE].views[0]);
/* Bind the image. */
struct pipe_image_view image = {0};
@ -461,7 +461,7 @@ void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex
if (is_array)
image.u.tex.last_layer = tex->array_size - 1;
ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, 0, &image);
ctx->set_shader_images(ctx, MESA_SHADER_COMPUTE, 0, 1, 0, &image);
/* Bind the shader. */
void **shader = &sctx->cs_fmask_expand[log_samples - 1][is_array];
@ -479,7 +479,7 @@ void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex
si_barrier_after_internal_op(sctx, 0, 0, NULL, 0, 1, &image);
/* Restore previous states. */
ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 1, 0, &saved_image);
ctx->set_shader_images(ctx, MESA_SHADER_COMPUTE, 0, 1, 0, &saved_image);
pipe_resource_reference(&saved_image.resource, NULL);
/* Array of fully expanded FMASK values, arranged by [log2(fragments)][log2(samples)-1]. */

36
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -520,7 +520,7 @@ static void si_set_sampler_views(struct si_context *sctx, unsigned shader,
samplers->needs_color_decompress_mask &= ~unbound_mask;
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(sctx, &sctx->atoms.s.gfx_shader_pointers);
}
@ -643,7 +643,7 @@ static void si_disable_shader_image(struct si_context *ctx, unsigned shader, uns
images->enabled_mask &= ~(1u << slot);
images->display_dcc_store_mask &= ~(1u << slot);
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(ctx, &ctx->atoms.s.gfx_shader_pointers);
}
}
@ -785,7 +785,7 @@ static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigne
images->display_dcc_store_mask |= 1u << slot;
/* Set displayable_dcc_dirty for non-compute stages conservatively (before draw calls). */
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
tex->displayable_dcc_dirty = true;
} else {
images->display_dcc_store_mask &= ~(1u << slot);
@ -799,7 +799,7 @@ static void si_set_shader_image(struct si_context *ctx, unsigned shader, unsigne
images->enabled_mask |= 1u << slot;
ctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(ctx, &ctx->atoms.s.gfx_shader_pointers);
/* Since this can flush, it must be done after enabled_mask is updated. */
@ -834,7 +834,7 @@ static void si_set_shader_images(struct pipe_context *pipe, enum pipe_shader_typ
for (i = 0; i < unbind_num_trailing_slots; ++i, ++slot)
si_set_shader_image(ctx, shader, slot, NULL, false);
if (shader == PIPE_SHADER_COMPUTE &&
if (shader == MESA_SHADER_COMPUTE &&
ctx->cs_shader_state.program &&
start_slot < ctx->cs_shader_state.program->sel.cs_num_images_in_user_sgprs)
ctx->compute_image_sgprs_dirty = true;
@ -998,7 +998,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx, enum pipe_shader_ty
si_set_sampler_state_desc(sstates[i], sview, tex, desc->list + desc_slot * 16 + 12);
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(sctx, &sctx->atoms.s.gfx_shader_pointers);
}
}
@ -1193,7 +1193,7 @@ void si_get_inline_uniform_state(union si_shader_key *key, enum pipe_shader_type
void si_invalidate_inlinable_uniforms(struct si_context *sctx, enum pipe_shader_type shader)
{
if (shader == PIPE_SHADER_COMPUTE)
if (shader == MESA_SHADER_COMPUTE)
return;
bool inline_uniforms;
@ -1246,7 +1246,7 @@ static void si_set_inlinable_constants(struct pipe_context *ctx,
{
struct si_context *sctx = (struct si_context *)ctx;
if (shader == PIPE_SHADER_COMPUTE)
if (shader == MESA_SHADER_COMPUTE)
return;
bool inline_uniforms;
@ -1345,7 +1345,7 @@ void si_set_shader_buffers(struct pipe_context *ctx, enum pipe_shader_type shade
assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
if (shader == PIPE_SHADER_COMPUTE &&
if (shader == MESA_SHADER_COMPUTE &&
sctx->cs_shader_state.program &&
start_slot < sctx->cs_shader_state.program->sel.cs_num_shaderbufs_in_user_sgprs)
sctx->compute_shaderbuf_sgprs_dirty = true;
@ -1716,7 +1716,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
si_const_and_shader_buffer_descriptors_idx(shader),
BITFIELD64_MASK(SI_NUM_SHADER_BUFFERS), buf,
sctx->const_and_shader_buffers[shader].priority) &&
shader == PIPE_SHADER_COMPUTE) {
shader == MESA_SHADER_COMPUTE) {
sctx->compute_shaderbuf_sgprs_dirty = true;
}
}
@ -1741,7 +1741,7 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
si_set_buf_desc_address(si_resource(buffer), samplers->views[i]->u.buf.offset,
descs->list + desc_slot * 16);
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(sctx, &sctx->atoms.s.gfx_shader_pointers);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer), RADEON_USAGE_READ |
@ -1773,14 +1773,14 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
si_set_buf_desc_address(si_resource(buffer), images->views[i].u.buf.offset,
descs->list + desc_slot * 8);
sctx->descriptors_dirty |= 1u << si_sampler_and_image_descriptors_idx(shader);
if (shader != PIPE_SHADER_COMPUTE)
if (shader != MESA_SHADER_COMPUTE)
si_mark_atom_dirty(sctx, &sctx->atoms.s.gfx_shader_pointers);
radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buffer),
RADEON_USAGE_READWRITE |
RADEON_PRIO_SAMPLER_BUFFER);
if (shader == PIPE_SHADER_COMPUTE)
if (shader == MESA_SHADER_COMPUTE)
sctx->compute_image_sgprs_dirty = true;
}
}
@ -2416,7 +2416,7 @@ void si_emit_compute_shader_pointers(struct si_context *sctx)
unsigned num_shaderbufs = shader->cs_num_shaderbufs_in_user_sgprs;
if (num_shaderbufs && sctx->compute_shaderbuf_sgprs_dirty) {
struct si_descriptors *desc = si_const_and_shader_buffer_descriptors(sctx, PIPE_SHADER_COMPUTE);
struct si_descriptors *desc = si_const_and_shader_buffer_descriptors(sctx, MESA_SHADER_COMPUTE);
radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 +
shader->cs_shaderbufs_sgpr_index * 4,
@ -2431,7 +2431,7 @@ void si_emit_compute_shader_pointers(struct si_context *sctx)
/* Set image descriptors in user SGPRs. */
unsigned num_images = shader->cs_num_images_in_user_sgprs;
if (num_images && sctx->compute_image_sgprs_dirty) {
struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, PIPE_SHADER_COMPUTE);
struct si_descriptors *desc = si_sampler_and_image_descriptors(sctx, MESA_SHADER_COMPUTE);
radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 +
shader->cs_images_sgpr_index * 4,
@ -2853,7 +2853,7 @@ static void si_emit_gfx_resources_add_all_to_bo_list(struct si_context *sctx, un
void si_init_all_descriptors(struct si_context *sctx)
{
int i;
unsigned first_shader = sctx->is_gfx_queue ? 0 : PIPE_SHADER_COMPUTE;
unsigned first_shader = sctx->is_gfx_queue ? 0 : MESA_SHADER_COMPUTE;
unsigned hs_sgpr0, gs_sgpr0;
if (sctx->gfx_level >= GFX12) {
@ -3077,7 +3077,7 @@ static void si_emit_gfx_resources_add_all_to_bo_list(struct si_context *sctx, un
bool si_compute_resources_check_encrypted(struct si_context *sctx)
{
unsigned sh = PIPE_SHADER_COMPUTE;
unsigned sh = MESA_SHADER_COMPUTE;
struct si_shader_info* info = &sctx->cs_shader_state.program->sel.info;
@ -3092,7 +3092,7 @@ bool si_compute_resources_check_encrypted(struct si_context *sctx)
void si_compute_resources_add_all_to_bo_list(struct si_context *sctx)
{
unsigned sh = PIPE_SHADER_COMPUTE;
unsigned sh = MESA_SHADER_COMPUTE;
si_buffer_resources_begin_new_cs(sctx, &sctx->const_and_shader_buffers[sh]);
si_sampler_views_begin_new_cs(sctx, &sctx->samplers[sh]);

2
src/gallium/drivers/radeonsi/si_get.c
View file

@ -927,7 +927,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
void si_init_shader_caps(struct si_screen *sscreen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&sscreen->b.shader_caps[i];

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -770,7 +770,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
}
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
unsigned start_shader = sctx->is_gfx_queue ? 0 : PIPE_SHADER_COMPUTE;
unsigned start_shader = sctx->is_gfx_queue ? 0 : MESA_SHADER_COMPUTE;
for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.set_constant_buffer(&sctx->b, shader, i, false, &sctx->null_const_buf);

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -110,7 +110,7 @@ struct ac_llvm_compiler;
#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
#define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
#define SI_SQTT_STATE_DIRTY_BIT BITFIELD_BIT(PIPE_SHADER_COMPUTE + 1)
#define SI_SQTT_STATE_DIRTY_BIT BITFIELD_BIT(MESA_SHADER_COMPUTE + 1)
enum si_has_gs {
GS_OFF,

2
src/gallium/drivers/radeonsi/si_query.c
View file

@ -1619,7 +1619,7 @@ static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_q
params.start_offset += qbuf->results_end - query->result_size;
}
sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, false, &constant_buffer);
sctx->b.set_constant_buffer(&sctx->b, MESA_SHADER_COMPUTE, 0, false, &constant_buffer);
ssbo[0].buffer = &qbuf->buf->b.b;
ssbo[0].buffer_offset = params.start_offset;

4
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -722,7 +722,7 @@ si_sqtt_pipe_to_rgp_shader_stage(union si_shader_key *key, enum pipe_shader_type
return RGP_HW_STAGE_GS;
case MESA_SHADER_FRAGMENT:
return RGP_HW_STAGE_PS;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return RGP_HW_STAGE_CS;
default:
UNREACHABLE("invalid mesa shader stage");
@ -752,7 +752,7 @@ si_sqtt_add_code_object(struct si_context *sctx,
enum rgp_hardware_stages hw_stage;
if (is_compute) {
if (i != PIPE_SHADER_COMPUTE)
if (i != MESA_SHADER_COMPUTE)
continue;
shader = &sctx->cs_shader_state.program->shader;
hw_stage = RGP_HW_STAGE_CS;

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1836,12 +1836,12 @@ static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
{
si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
si_get_pipe_constant_buffer(sctx, MESA_SHADER_COMPUTE, 0, &st->saved_const0);
}
void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
{
sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
sctx->b.set_constant_buffer(&sctx->b, MESA_SHADER_COMPUTE, 0, true, &st->saved_const0);
}
static void si_emit_db_render_state(struct si_context *sctx, unsigned index)

4
src/gallium/drivers/radeonsi/si_state.h
View file

@ -16,7 +16,7 @@ extern "C" {
#endif
#define SI_NUM_GRAPHICS_SHADERS (MESA_SHADER_FRAGMENT + 1)
#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE + 1)
#define SI_NUM_SHADERS (MESA_SHADER_COMPUTE + 1)
#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
#define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
@ -497,7 +497,7 @@ enum
#define SI_DESCS_INTERNAL 0
#define SI_DESCS_FIRST_SHADER 1
#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + MESA_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
#define SI_DESCS_SHADER_MASK(name) \

10
src/gallium/drivers/softpipe/sp_compute.c
View file

@ -199,7 +199,7 @@ softpipe_launch_grid(struct pipe_context *context,
for (local_z = 0; local_z < bdepth; local_z++) {
for (local_y = 0; local_y < bheight; local_y++) {
for (local_x = 0; local_x < bwidth; local_x += TGSI_QUAD_SIZE) {
machines[idx] = tgsi_exec_machine_create(PIPE_SHADER_COMPUTE);
machines[idx] = tgsi_exec_machine_create(MESA_SHADER_COMPUTE);
machines[idx]->LocalMem = local_mem;
machines[idx]->LocalMemSize = shared_mem_size;
@ -208,11 +208,11 @@ softpipe_launch_grid(struct pipe_context *context,
local_x, local_y, local_z,
grid_size[0], grid_size[1], grid_size[2],
bwidth, bheight, bdepth,
(struct tgsi_sampler *)softpipe->tgsi.sampler[PIPE_SHADER_COMPUTE],
(struct tgsi_image *)softpipe->tgsi.image[PIPE_SHADER_COMPUTE],
(struct tgsi_buffer *)softpipe->tgsi.buffer[PIPE_SHADER_COMPUTE]);
(struct tgsi_sampler *)softpipe->tgsi.sampler[MESA_SHADER_COMPUTE],
(struct tgsi_image *)softpipe->tgsi.image[MESA_SHADER_COMPUTE],
(struct tgsi_buffer *)softpipe->tgsi.buffer[MESA_SHADER_COMPUTE]);
tgsi_exec_set_constant_buffers(machines[idx], PIPE_MAX_CONSTANT_BUFFERS,
softpipe->mapped_constants[PIPE_SHADER_COMPUTE]);
softpipe->mapped_constants[MESA_SHADER_COMPUTE]);
idx++;
}
}

4
src/gallium/drivers/softpipe/sp_screen.c
View file

@ -200,7 +200,7 @@ softpipe_is_format_supported( struct pipe_screen *screen,
static void
softpipe_init_shader_caps(struct softpipe_screen *sp_screen)
{
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&sp_screen->base.shader_caps[i];
@ -213,7 +213,7 @@ softpipe_init_shader_caps(struct softpipe_screen *sp_screen)
}
FALLTHROUGH;
case MESA_SHADER_FRAGMENT:
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
tgsi_exec_init_shader_caps(caps);
break;
default:

2
src/gallium/drivers/softpipe/sp_state_derived.c
View file

@ -294,7 +294,7 @@ set_shader_sampler(struct softpipe_context *softpipe,
void
softpipe_update_compute_samplers(struct softpipe_context *softpipe)
{
set_shader_sampler(softpipe, PIPE_SHADER_COMPUTE, softpipe->cs->max_sampler);
set_shader_sampler(softpipe, MESA_SHADER_COMPUTE, softpipe->cs->max_sampler);
}
static void

16
src/gallium/drivers/svga/svga_draw.c
View file

@ -339,11 +339,11 @@ svga_validate_sampler_resources(struct svga_context *svga,
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = MESA_SHADER_VERTEX;
last_shader = PIPE_SHADER_COMPUTE;
last_shader = MESA_SHADER_COMPUTE;
}
else {
assert(svga_have_gl43(svga));
first_shader = PIPE_SHADER_COMPUTE;
first_shader = MESA_SHADER_COMPUTE;
last_shader = first_shader+1;
}
@ -422,11 +422,11 @@ svga_validate_constant_buffers(struct svga_context *svga,
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = MESA_SHADER_VERTEX;
last_shader = PIPE_SHADER_COMPUTE;
last_shader = MESA_SHADER_COMPUTE;
}
else {
assert(svga_have_gl43(svga));
first_shader = PIPE_SHADER_COMPUTE;
first_shader = MESA_SHADER_COMPUTE;
last_shader = first_shader + 1;
}
@ -524,10 +524,10 @@ svga_validate_image_views(struct svga_context *svga,
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = MESA_SHADER_VERTEX;
last_shader = PIPE_SHADER_COMPUTE;
last_shader = MESA_SHADER_COMPUTE;
}
else {
first_shader = PIPE_SHADER_COMPUTE;
first_shader = MESA_SHADER_COMPUTE;
last_shader = first_shader + 1;
}
@ -563,10 +563,10 @@ svga_validate_shader_buffers(struct svga_context *svga,
if (pipe_type == SVGA_PIPE_GRAPHICS) {
first_shader = MESA_SHADER_VERTEX;
last_shader = PIPE_SHADER_COMPUTE;
last_shader = MESA_SHADER_COMPUTE;
}
else {
first_shader = PIPE_SHADER_COMPUTE;
first_shader = MESA_SHADER_COMPUTE;
last_shader = first_shader + 1;
}

4
src/gallium/drivers/svga/svga_pipe_constants.c
View file

@ -76,7 +76,7 @@ svga_set_constant_buffer(struct pipe_context *pipe,
svga->dirty |= SVGA_NEW_TCS_CONSTS;
else if (shader == MESA_SHADER_TESS_EVAL)
svga->dirty |= SVGA_NEW_TES_CONSTS;
else if (shader == PIPE_SHADER_COMPUTE)
else if (shader == MESA_SHADER_COMPUTE)
svga->dirty |= SVGA_NEW_CS_CONSTS;
} else {
if (shader == MESA_SHADER_FRAGMENT)
@ -89,7 +89,7 @@ svga_set_constant_buffer(struct pipe_context *pipe,
svga->dirty |= SVGA_NEW_TCS_CONST_BUFFER;
else if (shader == MESA_SHADER_TESS_EVAL)
svga->dirty |= SVGA_NEW_TES_CONST_BUFFER;
else if (shader == PIPE_SHADER_COMPUTE)
else if (shader == MESA_SHADER_COMPUTE)
svga->dirty |= SVGA_NEW_CS_CONST_BUFFER;
/* update bitmask of dirty const buffers */

4
src/gallium/drivers/svga/svga_pipe_cs.c
View file

@ -48,7 +48,7 @@ svga_create_compute_state(struct pipe_context *pipe,
struct svga_shader *shader = &cs->base;
shader->id = svga->debug.shader_id++;
shader->type = PIPE_SHADER_IR_TGSI;
shader->stage = PIPE_SHADER_COMPUTE;
shader->stage = MESA_SHADER_COMPUTE;
/* Collect shader basic info */
svga_tgsi_scan_shader(&cs->base);
@ -73,7 +73,7 @@ svga_bind_compute_state(struct pipe_context *pipe, void *shader)
svga->dirty |= SVGA_NEW_CS;
/* Check if the shader uses samplers */
svga_set_curr_shader_use_samplers_flag(svga, PIPE_SHADER_COMPUTE,
svga_set_curr_shader_use_samplers_flag(svga, MESA_SHADER_COMPUTE,
svga_shader_use_samplers(&cs->base));
}

2
src/gallium/drivers/svga/svga_pipe_sampler.c
View file

@ -511,7 +511,7 @@ svga_cleanup_sampler_state(struct svga_context *svga)
{
enum pipe_shader_type shader;
for (shader = 0; shader <= PIPE_SHADER_COMPUTE; shader++) {
for (shader = 0; shader <= MESA_SHADER_COMPUTE; shader++) {
unsigned i;
for (i = 0; i < svga->state.hw_draw.num_sampler_views[shader]; i++) {

4
src/gallium/drivers/svga/svga_screen.c
View file

@ -256,7 +256,7 @@ vgpu10_init_shader_caps(struct svga_screen *svgascreen)
assert(sws->have_vgpu10);
for (unsigned i = 0; i <= PIPE_SHADER_COMPUTE; i++) {
for (unsigned i = 0; i <= MESA_SHADER_COMPUTE; i++) {
struct pipe_shader_caps *caps =
(struct pipe_shader_caps *)&svgascreen->screen.shader_caps[i];
@ -266,7 +266,7 @@ vgpu10_init_shader_caps(struct svga_screen *svgascreen)
if (!sws->have_sm5)
continue;
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
if (!sws->have_gl43)
continue;
break;

4
src/gallium/drivers/svga/svga_shader.c
View file

@ -473,7 +473,7 @@ svga_init_shader_key_common(const struct svga_context *svga,
/* Save the uavSpliceIndex which is the index used for the first uav
* in the draw pipeline. For compute, uavSpliceIndex is always 0.
*/
if (shader_type != PIPE_SHADER_COMPUTE)
if (shader_type != MESA_SHADER_COMPUTE)
key->uav_splice_index = svga->state.hw_draw.uavSpliceIndex;
unsigned uav_splice_index = key->uav_splice_index;
@ -791,7 +791,7 @@ svga_new_shader_variant(struct svga_context *svga, enum pipe_shader_type type)
case MESA_SHADER_TESS_CTRL:
variant = CALLOC(1, sizeof(struct svga_tcs_variant));
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
variant = CALLOC(1, sizeof(struct svga_cs_variant));
break;
default:

2
src/gallium/drivers/svga/svga_shader.h
View file

@ -542,7 +542,7 @@ svga_shader_type(enum pipe_shader_type shader)
return SVGA3D_SHADERTYPE_HS;
case MESA_SHADER_TESS_EVAL:
return SVGA3D_SHADERTYPE_DS;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return SVGA3D_SHADERTYPE_CS;
default:
assert(!"Invalid shader type");

18
src/gallium/drivers/svga/svga_state_constants.c
View file

@ -385,7 +385,7 @@ svga_get_extra_cs_constants(struct svga_context *svga, float *dest)
/* common constants */
count += svga_get_extra_constants_common(svga, variant,
PIPE_SHADER_COMPUTE,
MESA_SHADER_COMPUTE,
dest);
assert(count <= MAX_EXTRA_CONSTS);
@ -888,7 +888,7 @@ emit_consts_vgpu10(struct svga_context *svga, enum pipe_shader_type shader)
shader == MESA_SHADER_FRAGMENT ||
shader == MESA_SHADER_TESS_CTRL ||
shader == MESA_SHADER_TESS_EVAL ||
shader == PIPE_SHADER_COMPUTE);
shader == MESA_SHADER_COMPUTE);
cbuf = &svga->curr.constbufs[shader][0];
@ -913,7 +913,7 @@ emit_consts_vgpu10(struct svga_context *svga, enum pipe_shader_type shader)
variant = svga->state.hw_draw.tes;
extra_count = svga_get_extra_tes_constants(svga, (float *) extras);
break;
case PIPE_SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
variant = svga->state.hw_draw.cs;
extra_count = svga_get_extra_cs_constants(svga, (float *) extras);
break;
@ -1369,7 +1369,7 @@ emit_cs_consts(struct svga_context *svga, uint64_t dirty)
return PIPE_OK;
/* SVGA_NEW_CS_CONST_BUFFER */
ret = emit_consts_vgpu10(svga, PIPE_SHADER_COMPUTE);
ret = emit_consts_vgpu10(svga, MESA_SHADER_COMPUTE);
return ret;
}
@ -1389,7 +1389,7 @@ emit_cs_constbuf(struct svga_context *svga, uint64_t dirty)
/* SVGA_NEW_CS_CONSTBUF
*/
assert(svga_have_vgpu10(svga));
ret = emit_constbuf_vgpu10(svga, PIPE_SHADER_COMPUTE);
ret = emit_constbuf_vgpu10(svga, MESA_SHADER_COMPUTE);
return ret;
}
@ -1458,7 +1458,7 @@ update_rawbuf(struct svga_context *svga, uint64 dirty)
};
for (enum pipe_shader_type shader = MESA_SHADER_VERTEX;
shader < PIPE_SHADER_COMPUTE; shader++) {
shader < MESA_SHADER_COMPUTE; shader++) {
unsigned rawbuf_mask = svga->state.raw_constbufs[shader];
unsigned rawbuf_sbuf_mask = svga->state.raw_shaderbufs[shader];
@ -1496,15 +1496,15 @@ struct svga_tracked_state svga_need_rawbuf_srv =
static enum pipe_error
update_cs_rawbuf(struct svga_context *svga, uint64 dirty)
{
unsigned rawbuf_mask = svga->state.raw_constbufs[PIPE_SHADER_COMPUTE];
unsigned rawbuf_mask = svga->state.raw_constbufs[MESA_SHADER_COMPUTE];
update_rawbuf_mask(svga, PIPE_SHADER_COMPUTE);
update_rawbuf_mask(svga, MESA_SHADER_COMPUTE);
/* if the rawbuf state is different for the shader stage,
* send SVGA_NEW_RAW_BUFFER to trigger a new shader
* variant to use srv for ubo access.
*/
if (svga->state.raw_constbufs[PIPE_SHADER_COMPUTE] != rawbuf_mask)
if (svga->state.raw_constbufs[MESA_SHADER_COMPUTE] != rawbuf_mask)
svga->dirty |= SVGA_NEW_CS_RAW_BUFFER;
return PIPE_OK;

2
src/gallium/drivers/svga/svga_state_cs.c
View file

@ -27,7 +27,7 @@ make_cs_key(struct svga_context *svga,
memset(key, 0, sizeof *key);
svga_init_shader_key_common(svga, PIPE_SHADER_COMPUTE, &cs->base, key);
svga_init_shader_key_common(svga, MESA_SHADER_COMPUTE, &cs->base, key);
key->cs.grid_size[0] = svga->curr.grid_info.size[0];
key->cs.grid_size[1] = svga->curr.grid_info.size[1];

8
src/gallium/drivers/svga/svga_state_sampler.c
View file

@ -231,7 +231,7 @@ update_sampler_resources(struct svga_context *svga, uint64_t dirty)
assert(svga_have_vgpu10(svga));
for (shader = MESA_SHADER_VERTEX; shader < PIPE_SHADER_COMPUTE; shader++) {
for (shader = MESA_SHADER_VERTEX; shader < MESA_SHADER_COMPUTE; shader++) {
SVGA3dShaderResourceViewId ids[PIPE_MAX_SAMPLERS];
struct svga_winsys_surface *surfaces[PIPE_MAX_SAMPLERS];
struct pipe_sampler_view *sampler_views[PIPE_MAX_SAMPLERS];
@ -382,7 +382,7 @@ update_samplers(struct svga_context *svga, uint64_t dirty )
assert(svga_have_vgpu10(svga));
for (shader = MESA_SHADER_VERTEX; shader < PIPE_SHADER_COMPUTE; shader++) {
for (shader = MESA_SHADER_VERTEX; shader < MESA_SHADER_COMPUTE; shader++) {
const unsigned count = svga->curr.num_samplers[shader];
SVGA3dSamplerId ids[PIPE_MAX_SAMPLERS*2];
unsigned i;
@ -527,7 +527,7 @@ static enum pipe_error
update_cs_sampler_resources(struct svga_context *svga, uint64_t dirty)
{
enum pipe_error ret = PIPE_OK;
enum pipe_shader_type shader = PIPE_SHADER_COMPUTE;
enum pipe_shader_type shader = MESA_SHADER_COMPUTE;
assert(svga_have_sm5(svga));
@ -649,7 +649,7 @@ static enum pipe_error
update_cs_samplers(struct svga_context *svga, uint64_t dirty )
{
enum pipe_error ret = PIPE_OK;
enum pipe_shader_type shader = PIPE_SHADER_COMPUTE;
enum pipe_shader_type shader = MESA_SHADER_COMPUTE;
assert(svga_have_sm5(svga));

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