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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 13:38:06 +02:00
radeon/r200/r300: fix warnings
This commit is contained in:
parent
5021b47dd3
commit
f577c8e462
12 changed files with 17 additions and 47 deletions
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@ -112,7 +112,6 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
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GLuint primitive,
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GLuint vertex_nr )
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{
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drm_radeon_cmd_header_t *cmd;
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BATCH_LOCALS(&rmesa->radeon);
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assert(!(primitive & R200_VF_PRIM_WALK_IND));
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@ -164,8 +163,7 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type)
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void r200FlushElts(GLcontext *ctx)
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{
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r200ContextPtr rmesa = R200_CONTEXT(ctx);
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int dwords;
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r200ContextPtr rmesa = R200_CONTEXT(ctx);
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int nr, elt_used = rmesa->tcl.elt_used;
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if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
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@ -345,14 +343,3 @@ void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset)
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}
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END_BATCH();
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}
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void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type)
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{
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BATCH_LOCALS(&rmesa->radeon);
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BEGIN_BATCH(3);
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OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
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OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type);
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END_BATCH();
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}
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@ -243,7 +243,6 @@ static void r200_get_lock(radeonContextPtr radeon)
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{
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r200ContextPtr rmesa = (r200ContextPtr)radeon;
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drm_radeon_sarea_t *sarea = radeon->sarea;
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int i;
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R200_STATECHANGE( rmesa, ctx );
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if (rmesa->radeon.sarea->tiling_enabled) {
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@ -193,7 +193,6 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
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__DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
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GLuint flags = 0;
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GLuint color_mask = 0;
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GLint ret;
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GLuint orig_mask = mask;
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if ( R200_DEBUG & DEBUG_IOCTL ) {
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@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "main/macros.h"
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#include "main/context.h"
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#include "main/dd.h"
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#include "main/framebuffer.h"
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#include "main/simple_list.h"
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#include "main/api_arrayelt.h"
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#include "main/texformat.h"
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@ -2029,7 +2030,6 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
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static void r300ResetHwState(r300ContextPtr r300)
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{
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GLcontext *ctx = r300->radeon.glCtx;
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struct radeon_renderbuffer *rrb;
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int has_tcl = 1;
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if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
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@ -2039,7 +2039,6 @@ static void r300ResetHwState(r300ContextPtr r300)
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fprintf(stderr, "%s\n", __FUNCTION__);
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radeon_firevertices(&r300->radeon);
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//r300UpdateWindow(ctx);
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r300ColorMask(ctx,
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ctx->Color.ColorMask[RCOMP],
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@ -2524,9 +2523,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
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*/
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void r300InitState(r300ContextPtr r300)
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{
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GLcontext *ctx = r300->radeon.glCtx;
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GLuint depth_fmt;
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memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
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r300ResetHwState(r300);
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@ -36,6 +36,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "xmlpool.h" /* for symbolic values of enum-type options */
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#include "utils.h"
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#include "vblank.h"
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#include "drirenderbuffer.h"
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#include "main/state.h"
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#define DRIVER_DATE "20090101"
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@ -398,7 +399,7 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
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struct radeon_framebuffer *draw;
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radeonContextPtr radeon;
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char *regname;
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struct radeon_bo *depth_bo, *bo;
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struct radeon_bo *depth_bo = NULL, *bo;
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if (RADEON_DEBUG & DEBUG_DRI)
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fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
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@ -510,8 +510,9 @@ radeon_render_texture(GLcontext * ctx,
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att->TextureLevel);
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if (att->Texture->Target == GL_TEXTURE_3D) {
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const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt,
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att->TextureLevel);
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GLuint offsets[6];
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radeon_miptree_depth_offsets(radeon_image->mt, att->TextureLevel,
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offsets);
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imageOffset += offsets[att->Zoffset];
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}
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@ -61,7 +61,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
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__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
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__DRIdrawablePrivate *const readable = rmesa->dri.readable;
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__DRIscreenPrivate *sPriv = rmesa->dri.screen;
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drm_radeon_sarea_t *sarea = rmesa->sarea;
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assert(drawable != NULL);
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@ -92,7 +91,6 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
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void radeon_lock_hardware(radeonContextPtr radeon)
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{
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__DRIdrawable *dPriv = radeon->dri.drawable;
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char ret = 0;
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struct radeon_framebuffer *rfb = NULL;
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struct radeon_renderbuffer *rrb = NULL;
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@ -94,8 +94,6 @@ static void compute_tex_image_offset(radeon_mipmap_tree *mt,
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/* Find image size in bytes */
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if (mt->compressed) {
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/* TODO: Is this correct? Need test cases for compressed textures! */
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GLuint align;
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lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
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lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
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lvl->width, lvl->height, lvl->depth, mt->compressed);
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@ -365,14 +363,16 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
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*
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* These functions present that view to mesa:
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*/
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const GLuint *
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radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level)
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void
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radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets)
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{
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static const GLuint zero = 0;
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if (mt->target != GL_TEXTURE_3D || mt->faces == 1)
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return &zero;
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else
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return mt->levels[level].faces[0].offset;
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offsets[0] = 0;
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else {
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int i;
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for (i = 0; i < 6; i++)
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offsets[i] = mt->levels[level].faces[i].offset;
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}
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}
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GLuint
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@ -94,6 +94,5 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t,
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struct gl_texture_image *texImage, GLuint face, GLuint level);
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GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
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GLuint face, GLuint level);
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const GLuint *
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radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level);
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void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
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#endif /* __RADEON_MIPMAP_TREE_H_ */
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@ -377,7 +377,7 @@ do { \
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#include "stenciltmp.h"
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void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
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static void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
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{
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struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
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int r;
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@ -403,7 +403,6 @@ void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
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static void
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radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map)
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{
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radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
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GLuint i, j;
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/* color draw buffers */
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@ -825,6 +825,4 @@ void radeonInitSwtcl( GLcontext *ctx )
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void radeonDestroySwtcl( GLcontext *ctx )
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{
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r100ContextPtr rmesa = R100_CONTEXT(ctx);
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}
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@ -775,11 +775,6 @@ void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPri
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static void disable_tex_obj_state( r100ContextPtr rmesa,
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int unit )
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{
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/* do not use RADEON_DB_STATE to avoid stale texture caches */
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uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
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GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
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GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
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RADEON_STATECHANGE( rmesa, tex[unit] );
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RADEON_STATECHANGE( rmesa, tcl );
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@ -1142,8 +1137,6 @@ static GLboolean radeon_validate_texture(GLcontext *ctx, struct gl_texture_objec
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static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
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{
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r100ContextPtr rmesa = R100_CONTEXT(ctx);
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struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
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if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) {
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return GL_FALSE;
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