From f55d4f2f09f19f17895094265b4b99f03c4d6a5e Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 25 Jun 2024 10:56:49 +0200 Subject: [PATCH] radv: reserve space for push constants in the DGC ACE IB The upload space will be shared for both IBs when push constants need to be allocated. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_device_generated_commands.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 7f2f1ebf007..330c81e7943 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -160,12 +160,23 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout, struct struct radv_userdata_locations *locs = &pipeline->shaders[i]->info.user_sgprs_locs; if (locs->shader_data[AC_UD_PUSH_CONSTANTS].sgpr_idx >= 0) { /* One PKT3_SET_SH_REG for emitting push constants pointer (32-bit) */ - *cmd_size += 3 * 4; + if (i == MESA_SHADER_TASK) { + *ace_cmd_size += 3 * 4; + } else { + *cmd_size += 3 * 4; + } need_copy = true; } - if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) + if (locs->shader_data[AC_UD_INLINE_PUSH_CONSTANTS].sgpr_idx >= 0) { /* One PKT3_SET_SH_REG writing all inline push constants. */ - *cmd_size += (3 * util_bitcount64(layout->push_constant_mask)) * 4; + const uint32_t inline_pc_size = (3 * util_bitcount64(layout->push_constant_mask)) * 4; + + if (i == MESA_SHADER_TASK) { + *ace_cmd_size += inline_pc_size; + } else { + *cmd_size += inline_pc_size; + } + } } } else { /* Assume the compute shader needs both user SGPRs because we can't know the information