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intel/fs: Use a logical opcode for IMAGE_SIZE

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Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
This commit is contained in:
Jason Ekstrand 2018-10-31 09:52:33 -05:00 • committed by Jason Ekstrand
parent d2d3e04501
commit f547cebbe0
4 changed files with 21 additions and 6 deletions
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1
src/intel/compiler/brw_eu_defines.h
View file

@ -362,6 +362,7 @@ enum opcode {
SHADER_OPCODE_SAMPLEINFO_LOGICAL,
SHADER_OPCODE_IMAGE_SIZE,
SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
/**
* Combines multiple sources of size 1 into a larger virtual GRF.

10
src/intel/compiler/brw_fs.cpp
View file

@ -737,6 +737,7 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_TXF_LOGICAL:
case SHADER_OPCODE_TXL_LOGICAL:
case SHADER_OPCODE_TXS_LOGICAL:
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
case FS_OPCODE_TXB_LOGICAL:
case SHADER_OPCODE_TXF_CMS_LOGICAL:
case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
@ -4675,6 +4676,11 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_UD), lod);
length++;
break;
case SHADER_OPCODE_IMAGE_SIZE:
/* We need an LOD; just use 0 */
bld.MOV(retype(sources[length], BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
length++;
break;
case SHADER_OPCODE_TXF:
/* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
* On Gen9 they are u, v, lod, r
@ -5157,6 +5163,10 @@ fs_visitor::lower_logical_sends()
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXS);
break;
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_IMAGE_SIZE);
break;
case FS_OPCODE_TXB_LOGICAL:
lower_sampler_logical_send(ibld, inst, FS_OPCODE_TXB);
break;

14
src/intel/compiler/brw_fs_nir.cpp
View file

@ -3731,18 +3731,20 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
BRW_REGISTER_TYPE_UD);
image = bld.emit_uniformize(image);
fs_reg srcs[TEX_LOGICAL_NUM_SRCS];
srcs[TEX_LOGICAL_SRC_SURFACE] = image;
srcs[TEX_LOGICAL_SRC_SAMPLER] = brw_imm_d(0);
srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(0);
srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0);
/* Since the image size is always uniform, we can just emit a SIMD8
* query instruction and splat the result out.
*/
const fs_builder ubld = bld.exec_all().group(8, 0);
/* The LOD also serves as the message payload */
fs_reg lod = ubld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.MOV(lod, brw_imm_ud(0));
fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 4);
fs_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE, tmp, lod, image);
inst->mlen = 1;
fs_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
tmp, srcs, ARRAY_SIZE(srcs));
inst->size_written = 4 * REG_SIZE;
for (unsigned c = 0; c < instr->dest.ssa.num_components; ++c) {

2
src/intel/compiler/brw_shader.cpp
View file

@ -272,6 +272,8 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
case SHADER_OPCODE_IMAGE_SIZE:
return "image_size";
case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
return "image_size_logical";
case SHADER_OPCODE_SHADER_TIME_ADD:
return "shader_time_add";